US-12627286-B2 - Digital duty cycle corrector circuit

Abstract

A digital duty cycle corrector circuit is provided. The duty cycle corrector circuit includes a control circuit having a first transistor and a second transistor connected at a first node and configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node. A single to differential circuit is connected to the control circuit at the second node. The single to differential circuit generates a first output clock and a second output clock from the duty adjusted output clock. A feedback circuit configured to provide the duty adjusting output clock to a gate of each of the first transistor and the second transistor.

Inventors

• Chang-Yi Li

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260512

Application Date

20240627

Claims (20)

1. 1 . A digital duty cycle corrector circuit, comprising: a control circuit comprising a first transistor and a second transistor, wherein: a source/drain of the first transistor is connected to a first trim circuit, wherein the first trim circuit provides a first voltage at the source/drain of the first transistor, wherein the first trim circuit comprises a first plurality of transistors, and wherein each of the first plurality of transistors are connected in parallel to each other between a supply voltage node and the source/drain of the first transistor, a drain/source of the first transistor is connected to a drain/source of the second transistor at a first node, a source/drain of the second transistor is connected to a second trim circuit, wherein the second trim circuit provides a second voltage at the source/drain of the second transistor, the control circuit is configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node, and the control circuit further comprises a feedback circuit that connects the second node to a gate of each of the first transistor and the second transistor; and a single to differential circuit connected to the control circuit, wherein the single to differential circuit is configured to generate a first output clock and a second output clock from the duty adjusted output clock.
2. 2 . The digital duty cycle corrector circuit of claim 1 , wherein the second trim circuit comprises a second plurality of transistors, wherein each of the second plurality of transistors are connected in parallel to each other between the source/drain of the second transistor and a ground voltage node.
3. 3 . The digital duty cycle corrector circuit of claim 1 , wherein the feedback node comprises the second node.
4. 4 . The digital duty cycle corrector circuit of claim 1 , wherein the feedback node comprises another node in the single to differential circuit that is in a same phase as the second node.
5. 5 . The digital duty cycle corrector circuit of claim 1 , wherein an inverted clock signal is received at the first node.
6. 6 . The digital duty cycle corrector circuit of claim 1 , wherein the feedback node comprises another node on a first branch of the single to differential circuit that in a same phase as the second node.
7. 7 . The digital duty cycle corrector circuit of claim 1 , wherein the feedback node comprises another node on a second branch the single to differential circuit that in a same phase as the second node.
8. 8 . The digital duty cycle corrector circuit of claim 1 , wherein the control circuit further comprises an invertor connected between the first node and the second node.
9. 9 . A digital duty cycle corrector circuit, comprising: a control circuit comprising a first transistor and a second transistor connected at a first node and configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node; a single to differential circuit connected to the control circuit at the second node, wherein the single to differential circuit is configured to generate a first output clock and a second output clock from the duty adjusted output clock; and a feedback circuit configured to provide the duty adjusting output clock to a gate of each of the first transistor and the second transistor, wherein the feedback circuit connects another node in the single to differential circuit that in a same phase as the second node to the gate of each of the first transistor and the second transistor.
10. 10 . The digital duty cycle corrector circuit of claim 9 , wherein the control circuit further comprising: a first trim circuit connected to a source/drain of the first transistor, wherein the first trim circuit provides a first voltage at the source/drain of the first transistor; and a second trim circuit connected to a source/drain of the second transistor, wherein the second trim circuit provides a second voltage at the source/drain of the second transistor, and wherein a drain/source of the first transistor is connected to a drain/source of the second transistor at the first node.
11. 11 . The digital duty cycle corrector circuit of claim 9 , wherein the feedback circuit connects the second node to the gate of each of the first transistor and the second transistor.
12. 12 . The digital duty cycle corrector circuit of claim 9 , wherein the feedback circuit connects the another node on a first branch of the single to differential circuit that is in the same phase as the second node to the gate of each of the first transistor and the second transistor.
13. 13 . The digital duty cycle corrector circuit of claim 9 , wherein the control circuit further comprises an invertor connected between the first node and the second node.
14. 14 . The digital duty cycle corrector circuit of claim 9 , wherein the control circuit further comprises an invertor connected between the first node and the second node.
15. 15 . The digital duty cycle corrector circuit of claim 9 , wherein the first trim circuit comprises a first plurality of transistors, and wherein each of the first plurality of transistors are connected in parallel to each other between a supply voltage node and the source/drain of the first transistor.
16. 16 . The digital duty cycle corrector circuit of claim 9 , wherein the second trim circuit comprises a second plurality of transistors, wherein each of the second plurality of transistors are connected in parallel to each other between the source/drain of the second transistor and a ground voltage node.
17. 17 . A method of adjusting a duty cycle of an input clock, the method comprising: receiving an input clock at a first node of a control circuit comprising a first transistor and a second transistor connected at the first node; adjusting a duty cycle of the input clock based on a first trim code and a second trim code; providing a duty adjusted output clock at a second node of the control circuit; and providing the duty adjusted output clock as feedback at a gate of each of the first transistor and the second transistor of the control circuit, wherein providing the duty adjusted output clock as feedback at the gate of each of the first transistor and the second transistor of the control circuit comprises providing the duty adjusted output clock from another node in a single to differential circuit as feedback at the gate of each of the first transistor and the second transistor of the control circuit.
18. 18 . The method of claim 17 , further comprising: generating, by a single to differential circuit connected to the control circuit at the second node, a first output clock and a second output clock from the duty adjusted output clock.
19. 19 . The method of claim 17 , wherein the first trim circuit comprises a first plurality of transistors, and wherein each of the first plurality of transistors are connected in parallel to each other between a supply voltage node and the source/drain of the first transistor.
20. 20 . The method of claim 17 , wherein the second trim circuit comprises a second plurality of transistors, wherein each of the second plurality of transistors are connected in parallel to each other between the source/drain of the second transistor and a ground voltage node.

Description

BACKGROUND The number of high-speed circuits and high-speed systems continues to increase. Generally, the duty cycle of a clock signal in a high-speed circuit should be at fifty percent. However, due to variations in process, voltage, and temperature (PVT), the duty cycle of the clock signal is usually above or below fifty percent. In some instances, the duty cycle may deviate greatly from fifty percent, even when the duty cycle of the clock source is at fifty percent. Additionally, determining and applying corrections to a duty-cycle error can be challenging. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. In addition, the drawings are illustrative as examples of embodiments of the invention and are not intended to be limiting. FIG. 1 is a block diagram of a first example of a digital Duty Cycle Corrector (DCC) circuit in accordance with some embodiments. FIG. 2 is an example circuit diagram of the digital DCC circuit of FIG. 1 in accordance with some embodiments. FIG. 3 is an example illustration of duty cycle correction using the DCC circuit of FIG. 1 in accordance with some embodiments. FIG. 4 is example signal diagram of duty cycle correction using the DCC circuit of FIG. 1 in accordance with some embodiments. FIG. 5 is another example circuit diagram of the digital DCC circuit of FIG. 1 in accordance with some embodiments. FIG. 6 is an yet another example circuit diagram of the digital DCC circuit of FIG. 1 in accordance with some embodiments. FIG. 7 is a flow diagram of a method for adjusting a duty cycle of an input clock in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. A traditional analog duty-cycle corrector circuit uses an analog integrator to detect the duty cycle error. However, the analog integrator can only be used in low-speed applications. As compared to an analog duty-cycle corrector, a digital duty cycle corrector does not use the voltage control method, and thus it is less influenced by the leakage current of transistors. In addition, a digital duty cycle corrector operates in a lower voltage range. However, a digital duty cycle corrector suffers from inferior duty cycle linearity. Embodiments disclosed herein provide a digital Duty Cycle Corrector (DCC) circuit that produces a fifty percent (50%) duty cycle for a clock signal. Embodiments of a digital DCC circuit can be used in both low-speed and high-speed circuits and systems, including, for example, processing devices, memory input/output interfaces, and high-frequency data converters. Example processing devices include, but are not limited to, a central processing unit, a microprocessor, and a digital signal processor. In a non-limiting nonexclusive example, a digital DCC circuit can be implemented in, but are not limited to, a deskew circuit, a memory input/output interface, and/or a data converter circuit. The disclosed digital DCC circuit may operate on a broad frequency range of input signals and/or may accommodate a wide range of duty-cycle error. Additionally or alternatively, embodiments of the DCC circuit