US-12627292-B2 - Clamp circuits

Abstract

A clamp circuit including a first transistor having a control connection coupled to a first reference voltage terminal and a first controlled connection coupled to an input voltage terminal. The clamp circuit includes a second transistor having a control connection configured to receive a control voltage that is dependent on a current flowing through the first transistor, a first controlled connection coupled to the input voltage terminal, and a second controlled connection coupled to a second reference voltage terminal.

Inventors

• Dieter Draxelmayr
• Herwig Wappis

Assignees

• INFINEON TECHNOLOGIES AG

Dates

Publication Date

20260512

Application Date

20240320

Priority Date

20230405

Claims (18)

1. 1 . A clamp circuit comprising: a controlled current source having a first connection and a second connection; a first transistor having a control connection coupled to a first reference voltage terminal and having a first controlled connection and a second controlled connection coupled in series between an input voltage terminal and the first connection of the controlled current source, wherein the controlled current source is configured to generate a mirror current at the second connection of the controlled current source based on a current flowing through the first transistor; and a second transistor having a control connection coupled to the second connection of the controlled current source and configured to receive a control voltage that is dependent on the mirror current, having a first controlled connection coupled to the input voltage terminal, and having a second controlled connection coupled to a second reference voltage terminal.
2. 2 . The clamp circuit of claim 1 , wherein a voltage at the first reference voltage terminal is approximately equal to a voltage at the second reference voltage terminal.
3. 3 . The clamp circuit of claim 2 , wherein the first transistor and the second transistor are of identical conductivity type.
4. 4 . The clamp circuit of claim 1 , further comprising: a resistor coupling the control connection of the second transistor and the second connection of the controlled current source to a third reference voltage terminal, the resistor configured to provide the control voltage at the control connection of the second transistor.
5. 5 . The clamp circuit of claim 4 , wherein the controlled current source comprises a fourth reference voltage terminal, the clamp circuit further comprising: a first protection circuit coupled in series with the first transistor between the second controlled connection of the first transistor and the fourth reference voltage terminal, wherein a difference between a voltage at the control connection of the first transistor and a voltage at the second controlled connection of the first transistor is smaller than a predefined maximum voltage.
6. 6 . The clamp circuit of claim 5 , wherein the controlled current source comprises a fifth reference voltage terminal, wherein the first protection circuit comprises a first protective transistor coupled in series with the first transistor between the second controlled connection of the first transistor and the fourth reference voltage terminal, the first protective transistor having a control connection coupled to the fifth reference voltage terminal and configured to receive a supply voltage, wherein a difference between the supply voltage and a voltage at the first reference voltage terminal is smaller than the predefined maximum voltage.
7. 7 . The clamp circuit of claim 6 , further comprising: a second protection circuit coupled in series with the first transistor between the first controlled connection of the first transistor and the input voltage terminal, wherein a difference between the voltage at the control connection of the first transistor and a voltage at the first controlled connection of the first transistor is smaller than the predefined maximum voltage.
8. 8 . The clamp circuit of claim 7 , wherein the second protection circuit comprises a second protective transistor coupled in series with the first transistor between the first controlled connection of the first transistor and the input voltage terminal, the second protective transistor having a control connection coupled to the fifth reference voltage terminal and configured to receive the supply voltage.
9. 9 . The clamp circuit of claim 8 , further comprising: a third protection circuit coupled in series with the second transistor between the first controlled connection of the second transistor and the input voltage terminal, wherein a difference between a voltage at the control connection of the second transistor and a voltage at the first controlled connection of the second transistor is smaller than the predefined maximum voltage.
10. 10 . The clamp circuit of claim 9 , wherein the third protection circuit comprises a third protective transistor coupled in series with the second transistor between the first controlled connection of the second transistor and the input voltage terminal, the third protective transistor having a control connection coupled to the fifth reference voltage terminal and configured to receive the supply voltage, wherein a difference between the voltage at the control connection of the second transistor and the supply voltage is smaller than the predefined maximum voltage.
11. 11 . The clamp circuit of claim 10 , further comprising: a first current mirror transistor having a first controlled connection coupled to the fourth reference voltage terminal, having a second controlled connection coupled to the second controlled connection of the first transistor, and having a control connection coupled to the second controlled connection of the first current mirror transistor; and a second current mirror transistor coupled between a fourth protection circuit and the fourth reference voltage terminal and having a control connection coupled to the control connection of the first current mirror transistor, the fourth protection circuit coupled in series with the second current mirror transistor between a first controlled connection of the second current mirror transistor and the third reference voltage terminal, wherein a difference between a voltage at the control connection of the second current mirror transistor and a voltage at the first controlled connection of the second current mirror transistor is smaller than the predefined maximum voltage.
12. 12 . The clamp circuit of claim 11 , wherein the fourth protection circuit comprises a fourth protective transistor coupled between the fourth reference voltage terminal and the third reference voltage terminal, the fourth protective transistor being of a different conductivity type than the first transistor, the fourth protective transistor having a control connection configured to receive the supply voltage, wherein a difference between the voltage at the control connection of the second current mirror transistor and the supply voltage is smaller than the predefined maximum voltage.
13. 13 . The clamp circuit of claim 12 , further comprising: a fifth protective transistor coupled between the fourth protective transistor and the third reference voltage terminal, the fifth protective transistor being of a different conductivity type than the first transistor, the fifth protective transistor having a control connection coupled to the first reference voltage terminal.
14. 14 . The clamp circuit of claim 13 , further comprising: a sixth protective transistor coupled between the fourth protective transistor and the third reference voltage terminal, the sixth protective transistor having a control connection configured to receive the supply voltage.
15. 15 . The clamp circuit of claim 14 , wherein the predefined maximum voltage is less than or approximately equal to a usable operating voltage of the first transistor and/or a usable operating voltage of the second transistor, wherein a difference between a voltage at the input voltage terminal and the voltage at the first reference voltage terminal is greater than the usable operating voltage of the first transistor and/or the usable operating voltage of the second transistor.
16. 16 . A clamp circuit comprising: a current mirror circuit comprising a first transistor and a second transistor, the first transistor having a first current terminal coupled to a first reference voltage terminal, the second transistor having a first current terminal coupled to the first reference voltage terminal, the first transistor having a control terminal coupled to a control terminal of the second transistor and a second current terminal of the first transistor; a resistor having a first terminal coupled to a second current terminal of the second transistor and having a second terminal coupled to a second reference voltage terminal; a third transistor having a control terminal coupled to the second reference voltage terminal, having a first current terminal coupled to the second current terminal of the first transistor, and having a second current terminal coupled to an input voltage terminal; and a fourth transistor having a control terminal coupled to the first terminal of the resistor and the second current terminal of the second transistor, having a first current terminal coupled to the input voltage terminal, and having a second current terminal coupled to the second reference voltage terminal.
17. 17 . The clamp circuit of claim 16 , further comprising: a sixth transistor having a control terminal coupled to a third reference voltage terminal, and having a first current terminal and a second current terminal coupled in series between the second current terminal of the third transistor and the input voltage terminal; and a seventh transistor having a control terminal coupled to the third reference voltage terminal, and having a first current terminal and a second current terminal coupled in series between the first current terminal of the fourth transistor and the input voltage terminal.
18. 18 . The clamp circuit of claim 16 , further comprising: a sixth transistor having a control terminal coupled to a third reference voltage terminal, and having a first current terminal and a second current terminal coupled in series between the second current terminal of the first transistor and the first current terminal of the third transistor; and a seventh transistor having a control terminal coupled to the third reference voltage terminal, having a first current terminal coupled to the second current terminal of the second transistor, and having a second current terminal coupled to the first terminal of the resistor and the control terminal of the fourth transistor.

Description

REFERENCE TO RELATED APPLICATIONS This application claims priority to German Patent Application 10 2023 108 746.0, filed on Apr. 5, 2023, the contents of which are hereby incorporated by reference in their entirety. BACKGROUND It is occasionally necessary for high voltages to be handled by devices that do not have an appropriate rated voltage. One example of these is overvoltage-tolerant input/output interfaces. For example, a 5 V device (i.e., a device having a 5 V power supply and 5 V input/output interfaces) may use transistors that have a lower operating voltage than 5 V, e.g. 2.5 V. One problem is how to deal with overvoltages and undervoltages beyond the 5 V power supply. BRIEF DESCRIPTION OF THE DRAWINGS Exemplary embodiments of the disclosure are depicted in the figures and explained in more detail below. FIG. 1 shows a circuit based on various aspects of the present disclosure. FIG. 2 shows an example of an electrostatic discharge protection circuit. FIG. 3 shows a clamp circuit based on various aspects of the disclosure. FIG. 4 shows an example of the clamp circuit from FIG. 3 including an example implementation of the controlled current source. FIG. 5 shows another clamp circuit based on various aspects of the disclosure. FIG. 6 shows another clamp circuit based on various aspects of the disclosure. FIG. 7 shows another clamp circuit based on various aspects of the disclosure. DETAILED DESCRIPTION In the detailed description that follows, reference is made to the appended drawings, which form part of this description and which show specific embodiments of the disclosure for the purpose of illustration. It goes without saying that other embodiments can be used and structural or logical changes made without departing from the scope of protection of the present disclosure. It goes without saying that the features of the various illustrative embodiments described herein can be combined with one another unless specifically stated otherwise. The detailed description that follows should therefore not be regarded as restrictive, and the scope of protection of the present disclosure is defined by the attached claims. Within the context of this description, the terms “connected” and “coupled” are used to describe both a direct and an indirect connection and a direct or indirect coupling. In the figures, identical or similar elements are provided with identical reference signs where expedient. The disclosure relates to clamp circuits. In the case of analog inputs, the circuit is capable of processing supplied currents of +5 mA. The majority of this current flows into an electrostatic discharge (ESD) structure, for example, but with a 5.5 V power supply this would mean that the voltage at the input can be between approximately 6.5 V and −1 V when the temperature is low. This is potentially destructive for the connected circuit, for example because a gate oxide of connected transistors is designed only for ±3.6 V. Another problem that exists is an unsuitable voltage design of the transistors used in the device. Various aspects of this disclosure provide a circuit that consumes little to no current while an input voltage is within a predefined (e.g., permitted) range. Another aspect is diversion of the excess current coming from the outside to the most suitable rail of a circuit in order to save further energy. Positive currents (that, by way of example, flow into a device, for example into a chip) are routed to a positive supply rail (coupled with a second reference voltage terminal, e.g. VDD). Negative currents are routed to a negative rail (coupled with a first reference voltage terminal, e.g. ground (GND)). Another aspect of this disclosure is the use of “low-voltage transistors” in a “high-voltage environment”. A voltage clamp circuit for discharging input currents to the supply voltage terminal VDD or ground GND using a quasi-passive circuit is provided. The voltage clamp circuit activates itself when a transistor (e.g., a metal-oxide-semiconductor (MOS) transistor) threshold voltage is exceeded. Examples that are described here can relate to high voltages and low voltages. Some examples described here can relate to circuits for processing voltages in a range of approximately 5 V, while transistors that have a recommended operating voltage in a range of 2.5 V are used. In connection with these examples, 5 V can be understood as high voltage, while 2.5 V can be understood as low voltage. In connection with other examples described here, any desired voltage greater than a recommended operating voltage of a transistor or a usable operating voltage that is able to be used for transistors can be understood as high voltage, a voltage that is identical to or lower than the recommended operating voltage being able to be understood as low voltage. The recommended operating voltage may be a device-dependent (for example transistor-dependent) voltage or a device-dependent (for example transistor-dependent) potentia