Search

US-12627293-B2 - Semiconductor device

US12627293B2US 12627293 B2US12627293 B2US 12627293B2US-12627293-B2

Abstract

A semiconductor device includes a first and a second output transistor on a high and a low side respectively, a first terminal connected to the connection node between the first and second output transistors, and a second terminal configured to be connected via a bootstrap capacitor to the first terminal. The first output transistor is driven based on a voltage between the first and second terminals. A switching circuit is provided between a terminal fed with a predetermined control supply voltage and the second terminal. The switching circuit includes a first and a second switching element, which are N-channel MOSFETs connected in series. According to the voltage at the first terminal, the first and second switching elements are turned on or off.

Inventors

  • Hideo Hara

Assignees

  • ROHM CO., LTD.

Dates

Publication Date
20260512
Application Date
20240228
Priority Date
20210830

Claims (6)

  1. 1 . A semiconductor device, comprising: a first output transistor; a second output transistor connected, at a low-potential side of the first output transistor, in series with the first output transistor; a first terminal connected to a connection node between the first and second output transistors; a second terminal configured to be connected via a bootstrap capacitor to the first terminal; a first driver configured to drive the first output transistor based on a voltage between the first and second terminals; a second driver configured to drive the second output transistor; a first switching element configured with an N-channel MOSFET having a source connected to the second terminal; a second switching element configured with an N-channel MOSFET having a source fed with a predetermined control supply voltage and a drain connected to a drain of the first switching element; a switching control circuit configured to turn the first and second switching elements on or off according to a voltage at the first terminal; a first charge pump circuit having a first output node, the first charge pump circuit being capable of generating at the first output node a first boosted voltage higher than a voltage at the second terminal by performing first charge pump operation based on the voltage at the second terminal relative to a potential at the first terminal; and a second charge pump circuit having a second output node, the second charge pump circuit being capable of generating at the second output node a second boosted voltage higher than the control supply voltage by performing second charge pump operation based on the control supply voltage relative to a ground potential, wherein the first output node is connected to a gate of the first switching element, the second output node is connected to a gate of the second switching element, the switching control circuit is configured to turn the first switching element on by making the first charge pump circuit perform the first charge pump operation, and turn the second switching element on by making the second charge pump circuit perform the second charge pump operation.
  2. 2 . The semiconductor device according to claim 1 , wherein when the voltage at the first terminal has a negative polarity, the switching control circuit switches the first switching element between on and off according to a differential voltage between the first and second terminals relative to a potential at the first terminal.
  3. 3 . The semiconductor device according to claim 2 , wherein when the voltage at the first terminal has a negative polarity, the switching control circuit keeps the first switching element on if the differential voltage is lower than a predetermined voltage and keeps the first switching element off if the differential voltage is higher than the predetermined voltage.
  4. 4 . The semiconductor device according to claim 1 , wherein the switching control circuit keeps the second switching element off if the voltage at the first terminal is higher than a positive threshold voltage.
  5. 5 . The semiconductor device according to claim 1 , wherein the switching control circuit keeps the first and second switching elements on if the first output transistor is off and the second output transistor is on.
  6. 6 . The semiconductor device according to claim 1 , wherein the second output transistor is provided between the first terminal and a reference conductor at a ground potential.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This nonprovisional application is a continuation application of International Patent Application No. PCT/JP2022/024328 filed on Jun. 17, 2022, which claims priority Japanese Patent Applications No. 2021-139893, No. 2021-139895, No. 2021-139898, No. 2021-139899, and No. 2021-139902 all filed on Aug. 30, 2021, the entire contents of which are hereby incorporated by reference. TECHNICAL FIELD The present disclosure relates to semiconductor devices. BACKGROUND ART A bootstrap circuit including a bootstrap capacitor is used to drive a high-side transistor in a half-bridge circuit. In a device that includes a bootstrap circuit, generally, one terminal of a bootstrap capacitor is connected to a connection node between a high-side transistor and a low-side transistor and the other terminal of the bootstrap capacitor is connected to the cathode of a bootstrap diode. The anode of the bootstrap diode is fed with a predetermined voltage. Based on the charge voltage of the bootstrap capacitor, the high-side transistor is driven. As the potential at the above-mentioned connection node varies as a result of the high-side and low-side transistors being switched, the bootstrap capacitor is charged. CITATION LIST Patent Literature Patent Document 1: JP-A-2018-19498 BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is an overall configuration diagram of a load driving system according to a first embodiment of the present disclosure. FIG. 2 is an exterior perspective view of a semiconductor device according to the first embodiment of the present disclosure. FIG. 3 is a diagram showing the waveforms of signals and the like associated with the semiconductor device in connection with the first embodiment of the present disclosure. FIG. 4 is a diagram showing the flow of a current in a both-off period in connection with the first embodiment of the present disclosure. FIG. 5 is a diagram showing the flow of a current in a both-off period in connection with the first embodiment of the present disclosure. FIG. 6 is a diagram showing a configuration involved in the generation of a boot voltage in connection with the first embodiment of the present disclosure. FIG. 7 is a timing chart associated with the on/off control of transistors in a switching circuit in connection with the first embodiment of the present disclosure. FIG. 8 is a timing chart associated with the on/off control of transistors in a switching circuit in connection with the first embodiment of the present disclosure. FIG. 9 is a diagram showing a configuration involved in the generation of a boot voltage in connection with a reference example. FIG. 10 is a diagram showing the waveforms of voltages and a current according to the reference example. FIG. 11 is a diagram showing the waveforms of voltages and a current according to the first embodiment of the present disclosure. FIG. 12 is a diagram showing the relationship among a plurality of periods, a plurality of detection signals, and the state of a switching circuit in connection with the first embodiment of the present disclosure. FIG. 13 is a timing chart according to the first embodiment of the present disclosure. FIG. 14 is a diagram showing the configuration of part of a semiconductor device in connection with a second embodiment of the present disclosure. FIG. 15 is a circuit diagram of a negative voltage detection circuit in connection with the second embodiment of the present disclosure. FIG. 16 is a diagram showing two current paths provided in the negative voltage detection circuit in connection with the second embodiment of the present disclosure. FIG. 17 is a diagram illustrating a static state of the negative voltage detection circuit in connection with the second embodiment of the present disclosure. FIG. 18 is a diagram illustrating a static state of the negative voltage detection circuit in connection with the second embodiment of the present disclosure. FIG. 19 is a diagram illustrating a state transition of the negative voltage detection circuit in connection with the second embodiment of the present disclosure. FIG. 20 is a diagram illustrating a state transition of the negative voltage detection circuit in connection with the second embodiment of the present disclosure. FIG. 21 is a diagram illustrating a state transition of the negative voltage detection circuit in connection with the second embodiment of the present disclosure. FIG. 22 is a diagram schematically showing an outline of the waveforms of some signals associated with the negative voltage detection circuit in connection with the second embodiment of the present disclosure. FIG. 23 is a diagram schematically showing an outline of the waveforms of some signals associated with an imaginary negative voltage detection circuit in connection with the second embodiment of the present disclosure. FIG. 24 is a diagram showing a modified configuration of the negative voltage detection circuit in connection with the se