US-12627296-B2 - Programmable logic circuit

US12627296B2US 12627296 B2US12627296 B2US 12627296B2US-12627296-B2

Abstract

The application discloses a programmable logic circuit, which comprising: a first lookup table circuit for generating and outputting a first output signal based on a received input signal; a second lookup table circuit for generating a carry propagation signal and a carry generation signal based on a received input signal, selecting one of the signals as the output; a first selection circuit for receiving a carry input signal and a carry generation signal, selecting one of the signals as the output based on the carry propagation signal; a second selection circuit for receiving a first output signal and a second output signal, selecting one of the signals as the output based on the selection output signal. The circuit provided in this application includes the addition operation of multivariate functions, which improves the configuration flexibility and logic resource utilization efficiency of programmable logic devices in addition operation mode.

Inventors

Changlong WANG
Peifu Shen
Kang Yu
Beibei LIU
Heng Zhang
Min Zhang
Qipan FU

Assignees

SHENZHEN PANGO MICROSYSTEMS CO.,LTD

Dates

Publication Date: 20260512
Application Date: 20240501
Priority Date: 20230506

Claims (11)

1 . A programmable logic circuit, comprising: a first lookup table circuit, the first lookup table circuit is used for generating a first output signal based on a received input signal and outputting the first output signal; a second lookup table circuit, the second lookup table circuit is used for generating and outputting a carry propagation signal and a carry generation signal based on a received input signal, and selecting the carry propagation signal or the carry generation signal as a second output signal to output; a first selection circuit, the first selection circuit is used for receiving a carry input signal and the carry generation signal, and selecting the carry input signal or the carry generation signal as a carry output signal based on the carry propagation signal; a second selection circuit, the second selection circuit is used for receiving the first output signal and the second output signal, and selecting the first output signal or the second output signal as a third output signal based on a selection output signal.
2 . The programmable logic circuit of claim 1 , wherein the first lookup table circuit comprises a first five input lookup table and a third selection circuit, the first to fourth input ends of the first five input lookup table are respectively used for receiving the first to fourth input signals, a fifth input end of the first five input lookup table is used for receiving a signal output by the third selection circuit, an output end of the first five input lookup table is used for outputting the first output signal; the third selection circuit is used for receiving a fifth input signal and the carry input signal, and selecting the fifth input signal or the carry input signal to output.
3 . The programmable logic circuit of claim 2 , wherein the third selection circuit is also used for receiving a cascade input signal to select one of the cascade input signal, the fifth input signal, and the carry input signal to output to a fifth input end of the first five input lookup table; the second selection circuit is also used for using the selected the first output signal or the second output signal as a cascade output signal.
4 . The programmable logic circuit of claim 1 , wherein the second lookup table circuit comprises: a second five input lookup table, the first to fourth input ends of the second five input lookup table are respectively used for receiving the first to fourth input signals, a fifth input end of the second five input lookup table is used for receiving a fifth input signal, a first output end of the second five input lookup table is used for outputting the carry propagation signal, a second output end of the second five input lookup table is used for outputting the carry generation signal, and a third output end of the second five input lookup table is used for outputting the second output signal.
5 . The programmable logic circuit of claim 4 , wherein the second lookup table circuit further comprises: a fourth selection circuit, the fourth selection circuit is used for receiving the fifth input signal and a cascade input signal, selecting the fifth input signal or the cascade input signal to output, the signal output from the fourth selection circuit is used for determining the signal output from the third output end of the second five input lookup table.
6 . The programmable logic circuit of claim 5 , wherein the fourth selection circuit is also used for receiving a sixth input signal to select one of the sixth input signal, the fifth input signal, and the cascade input signal to output to a fifth input end of the second five input lookup table.
7 . The programmable logic circuit of claim 1 , wherein the first selection circuit comprises: a first multiplexer, a first input end of the first multiplexer for receiving the carry generation signal, a second input end of the first multiplexer for receiving the second output signal, a selection end of the first multiplexer for receiving the carry propagation signal, and an output end of the first multiplexer for selecting the carry generation signal or the carry input signal as a carry output signal to output based on the carry propagation signal; the second selection circuit comprises: a second multiplexer, a first input end of the second multiplexer for receiving the first output signal, a second input of the second multiplexer for receiving the second output signal, a selection end of the second multiplexer for receiving the selection output signal, and the output end of the second multiplexer for selecting the first output signal or the second output signal as a third output signal to output based on the selection output signal.
8 . The programmable logic circuit of claim 3 , wherein the third selection circuit comprises: a third multiplexer, a first input end of the third multiplexer for receiving the fifth input signal, a second input end of the third multiplexer for receiving the carry input signal, and a third input end of the third multiplexer for receiving the cascade input signal, an output end of the third multiplexer for selecting one of the fifth input signal, the carry input signal, and the cascade input signal to output to the fifth input end of the first five input lookup table.
9 . The programmable logic circuit of claim 6 , wherein the fourth selection circuit comprises: a fourth multiplexer, a first input end of the fourth multiplexer for receiving the fifth input signal, a second input end of the fourth multiplexer for receiving the sixth input signal, a third input end of the fourth multiplexer for receiving the cascade input signal, and an output of the fourth multiplexer for selecting one of the fifth input signal, the sixth input signal, and the cascade input signal to output to a fifth input of the second five input lookup table.
10 . The programmable logic circuit of claim 8 , wherein the selection ends of the third multiplexer and the fourth multiplexer are both programmed to control the signal output from their output end, the programming methods of the selection ends at least include SRAM programming, Flash programming, fuse programming and anti fuse programming.
11 . The programmable logic circuit of claim 9 , wherein the selection ends of the third multiplexer and the fourth multiplexer are both programmed to control the signal output from their output end, the programming methods of the selection ends at least include SRAM programming, Flash programming, fuse programming and anti fuse programming.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Chinese Patent Application No. CN202310506585.3, filed on May 6, 2023, the entire contents of which are incorporated herein by reference. FIELD OF THE DISCLOSURE The invention relates to the field of programmable integrated circuit technology, specifically to a programmable logic circuit. BACKGROUND The programmable logic circuit based on look up table (LUT) is the basic logic module of programmable logic device, it has the advantages of short development cycle, low cost, small risk, high integration, and great flexibility, and is widely used in communication, internet, automobile, aerospace and other fields. The existing programmable logic circuit is shown in FIG. 1, when the programmable logic circuit is used as an adder, the carry input signal of the adder can only be input from port A4, resulting in the need to consume logic resources outside of the programmable logic circuit when the carry generation signal of the programmable logic circuit is a multivariate function, resulting in low resource utilization efficiency. SUMMARY In view of the above issues, this application provides a programmable logic circuit to solve the above mentioned technical problems. A programmable logic circuit, comprises: a first lookup table circuit, the first lookup table circuit is used for generating a first output signal based on a received input signal and outputting the first output signal;a second lookup table circuit, the second lookup table circuit is used for generating and outputting a carry propagation signal and a carry generation signal based on a received input signal, and selecting the carry propagation signal or the carry generation signal as a second output signal to output;a first selection circuit, the first selection circuit is used for receiving a carry input signal and the carry generation signal, and selecting the carry input signal or the carry generation signal as a carry output signal based on the carry propagation signal;a second selection circuit, the second selection circuit is used for receiving the first output signal and the second output signal, and selecting the first output signal or the second output signal as a third output signal based on the selection output signal. Further, the first lookup table circuit comprises a first five input lookup table and a third selection circuit, the first to fourth input ends of the first five input lookup table are respectively used for receiving the first to fourth input signals, a fifth input end of the first five input lookup table for receiving a signal output by the third selection circuit, an output end of the first five input lookup table is used for outputting the first output signal;the third selection circuit is used for receiving a fifth input signal and the carry input signal, and to selecting the fifth input signal or the carry input signal to output. Further, the third selection circuit is also used for receiving a cascade input signal to select one of the cascade input signal, the fifth input signal, and the carry input signal to output to a fifth input end of the first five input lookup table; the second selection circuit is also used for using the selected the first output signal or the second output signal as a cascade output signal. Further, the second lookup table circuit comprises: a second five input lookup table, the first to fourth input ends of the second five input lookup table are respectively used for receiving the first to fourth input signals, a fifth input end of the second five input lookup table is used for receiving a fifth input signal, a first output end of the second five input lookup table is used for outputting the carry propagation signal, a second output end of the second five input lookup table is used for outputting the carry generation signal, and a third output end of the second five input lookup table is used for outputting the second output signal. Further, the second lookup table circuit further comprises: a fourth selection circuit, the fourth selection circuit is used for receiving the fifth input signal and a cascade input signal, selecting the fifth input signal or the cascade input signal to output, the signal output from the fourth selection circuit is used for determining the signal output from the third output end of the second five input lookup table. Further, the fourth selection circuit is also used for receiving a sixth input signal to select one of the sixth input signal, the fifth input signal, and the cascade input signal to output to a fifth input end of the second five input lookup table. Further, the first selection circuit comprises: a first multiplexer, a first input end of the first multiplexer for receiving the carry generation signal, a second input end of the first multiplexer for receiving the second output signal, a selection end of the first multiplexer for receiving the carry propagation signal, and an outp