US-12627297-B2 - Strong PUF circuit capable of implementing multi-bit parallel XOR operations

US12627297B2US 12627297 B2US12627297 B2US 12627297B2US-12627297-B2

Abstract

A strong PUF circuit capable of implementing multi-bit parallel XOR operations comprises a presetting module, an interleaving module, a cascading module and a control module, wherein the control module controls the operating mode of the strong PUF circuit capable of implementing multi-bit parallel XOR operations to allow the strong PUF circuit capable of implementing multi-bit parallel XOR operations to operate in a PUF mode, a logic operation mode or a power control mode; when operating in the PUF mode, the strong PUF circuit capable of implementing multi-bit parallel XOR operations functions as a PUF circuit; when operating in the logic operation mode, the strong PUF circuit capable of implementing multi-bit parallel XOR operations realizes an XOR operation logic function; and when operating in the power control mode, the strong PUF circuit capable of implementing multi-bit parallel XOR operations realizes low-power standby.

Inventors

Gang Li
Pengjun WANG
Junjie Zhou
Hui Li
Hao YE

Assignees

WENZHOU UNIVERSITY

Dates

Publication Date: 20260512
Application Date: 20240924
Priority Date: 20240614

Claims (9)

1 . A strong PUF circuit capable of implementing multi-bit parallel XOR operations, comprising a presetting module, an interleaving module, a cascading module and a control module, wherein the control module is used for controlling an operating mode of the strong PUF circuit capable of implementing multi-bit parallel XOR operations, and under the control of the control module, the strong PUF circuit capable of implementing multi-bit parallel XOR operations is able to operate in a PUF mode, a logic operation mode or a power control mode; in response to the strong PUF circuit capable of implementing multi-bit parallel XOR operations operates in the PUF mode, the cascading module is used for controlling the presetting module to generate two reverse response values, and the interleaving module is used for alternately selecting the two response values generated by the presetting module as PUF response outputs of the strong PUF circuit capable of implementing multi-bit parallel XOR operations; in response to the strong PUF circuit capable of implementing multi-bit parallel XOR operations operates in the logic operation mode, the cascading module is used for inputting XOR operation data, controlling the presetting module to generate an XOR operation result and an XNOR operation result and outputting the XOR operation result and the XNOR operation result; and in response to the strong PUF circuit capable of implementing multi-bit parallel XOR operations operates in the power control mode, low-power operation of the strong PUF circuit capable of implementing multi-bit parallel XOR operations is realized.
2 . A strong PUF circuit capable of implementing multi-bit parallel XOR operations according to claim 1 , wherein in response to the strong PUF circuit capable of implementing multi-bit parallel XOR operations operates in the PUF mode, the presetting module is able to improve the stability of the two generated response values by screening out instable bits, so as to reduce the bit error rate.
3 . A strong PUF circuit capable of implementing multi-bit parallel XOR operations according to claim 2 , wherein the presetting module has a power terminal, a pre-charge terminal, n left screening signal input terminals, n right screening signal input terminals and two output terminals, wherein n is an integer which is greater than or equal to 1, the two output terminals of the presetting module are referred to as a first output terminal and a second output terminal respectively, an operating supply voltage VDD is accessed to the power terminal of the presetting module, a pre-charge signal PRE is input to the pre-charge terminal of the presetting module, n left screening signals SL 1 -SLn are input to the n left screening signal input terminals of the presetting module, and n right screening signals SR 1 -SRn are input to the n right screening signal input terminals of the presetting module; the interleaving module has two input terminals, a selection signal input terminal and an output terminal, the two input terminals of the interleaving module are referred to as a first input terminal and a second input terminal respectively, and a clock signal SW is input to the selection signal input terminal of the interleaving module; wherein the cascading module has n signal input terminals, two input terminals and two output terminals, the two input terminals of the cascading module are referred to as a first input terminal and a second input terminal respectively, and the two output terminals of the cascading module are referred to a first output terminal and a second output terminal respectively; wherein the control module has two input terminals, two control terminals, a pre-charge terminal and a ground terminal, the two input terminals of the control module are referred to a first input terminal and a second input terminal respectively, the two control terminals of the control module are referred to a first control terminal and a second control terminal respectively, a first control signal X is input to the first control terminal of the control module, a second control signal Y is input to the second control terminal of the control module, the pre-charge signal PRE is input to the pre-charge terminal of the control module, and a ground voltage VSS is accessed to the ground terminal of the control module; the first output terminal of the presetting module is connected to the first input terminal of the interleaving module and the first input terminal of the cascading module, the second output terminal of the presetting module is connected to the second input terminal of the interleaving module and the second input terminal of the cascading module, the first output terminal of the cascading module is connected to the first input terminal of the control module, and the second output terminal of the cascading module is connected to the second input terminal of the control module; wherein in response to the strong PUF circuit capable of implementing multi-bit parallel XOR operations operates in the logic operation mode, the n signal input terminals of the cascading module function as n data input terminals of the strong PUF circuit capable of implementing multi-bit parallel XOR operations and allow the XOR operation data to be input thereto, the first output terminal of the presetting module functions as a first output terminal of the strong PUF circuit capable of implementing multi-bit parallel XOR operations and is used for outputting the XOR operation result or the XNOR operation result, and the second output terminal of the presetting module functions as a second output terminal of the strong PUF circuit capable of implementing multi-bit parallel XOR operations and is used for outputting the XNOR operation result or the XOR operation result; and in the case where the strong PUF circuit capable of implementing multi-bit parallel XOR operations operates in the PUF mode, the n signal input terminals of the cascading module function as n challenge terminals of the strong PUF circuit capable of implementing multi-bit parallel XOR operations and allow challenge signals to be input thereto, and the output terminal of the interleaving module functions as a PUF response output terminal of the strong PUF circuit capable of implementing multi-bit parallel XOR operations and is used for outputting PUF responses.
4 . A strong PUF circuit capable of implementing multi-bit parallel XOR operations according to claim 3 , wherein the presetting module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, n left screening cells and n right screening cells; wherein each left screening cell has a power terminal, two input terminals and an output terminal, and the two input terminals of the left screening cell are referred to as a first input terminal and a second input terminal respectively; wherein each right screening cell has a power terminal, two input terminals and an output terminal, and the two input terminals of the right screening cell are referred to as a first input terminal and a second input terminal respectively; wherein a source of the first PMOS transistor, a source of the second PMOS transistor, a source of the third PMOS transistor, a source of the fourth PMOS transistor, the power terminals of the n left screening cells and the power terminals of the n right screening cells are connected and a connecting terminal is the power terminal of the presetting module, a gate of the third PMOS transistor and a gate of the fourth PMOS transistor are connected and a connecting terminal is the pre-charge terminal of the presetting module, the first input terminals of the n left screening cells are the n left screening signal input terminals of the presetting module, the first input terminals of the n right screening cells are the n right screening signal input terminals of the presetting module, a drain of the first PMOS transistor, a gate of the second PMOS transistor, a drain of the third PMOS transistor, the second input terminals of the n right screening cells and the output terminals of the n left screening cells are connected and a connecting terminal is the first output terminal of the presetting module, and a drain of the second PMOS transistor, a gate of the first PMOS transistor, a drain of the fourth PMOS transistor, the output terminals of the n right screening cells and the second input terminals of the n left screening cells are connected and a connecting terminal is the second output terminal of the presetting module.
5 . A strong PUF circuit capable of implementing multi-bit parallel XOR operations according to claim 4 , wherein each left screening cell comprises a fifth PMOS transistor and a sixth PMOS transistor, wherein a source of the fifth PMOS transistor is the power terminal of the left screening cell, a gate of the fifth PMOS transistor is the first input terminal of the left screening cell, a drain of the fifth PMOS transistor and a source of the sixth PMOS transistor are connected, a gate of the sixth PMOS transistor is the second input terminal of the left screening cell, and a drain of the sixth PMOS transistor is the output terminal of the left screening cell; wherein each right screening cell comprises a seventh PMOS transistor and an eighth PMOS transistor, wherein a source of the seventh PMOS transistor is the power terminal of the right screening cell, a gate of the seventh PMOS transistor is the first input terminal of the right screening cell, a drain of the seventh PMOS transistor and a source of the eighth PMOS transistor are connected, a gate of the eighth PMOS transistor is the second input terminal of the right screening cell, and a drain of the eighth PMOS transistor is the output terminal of the right screening cell.
6 . A strong PUF circuit capable of implementing multi-bit parallel XOR operations according to claim 3 , wherein the interleaving module comprises a first inverter, a second inverter, a third inverter, a first NMOS transistor, a second NMOS transistor, a ninth PMOS transistor and a tenth PMOS transistor, wherein an input terminal of the first inverter is the first input terminal of the interleaving module, an input terminal of the second inverter is the second input terminal of the interleaving module, an output terminal of the first inverter, a drain of the first NMOS transistor and a source of the ninth PMOS transistor are connected, an output terminal of the second inverter, a drain of the second NMOS transistor and a source of the tenth PMOS transistor are connected, a gate of the first NMOS transistor and a gate of the tenth PMOS transistor are connected and a connecting terminal is the selection signal input terminal of the interleaving module, a gate of the ninth PMOS transistor and a gate of the second NMOS transistor are connected, a source of the first NMOS transistor, a drain of the ninth PMOS transistor, a source of the second NMOS transistor, a drain of the tenth PMOS transistor and an input terminal of the third inverter are connected, and an output terminal of the third inverter is the output terminal of the interleaving module.
7 . A strong PUF circuit capable of implementing multi-bit parallel XOR operations according to claim 3 , wherein the cascading module comprises n deviation cells, wherein each deviation cell has a signal input terminal, a first input terminal, a second input terminal, a first output terminal and a second output terminal, the signal input terminals of the n deviation cells are the n signal input terminals of the cascading module, the first input terminal of the first deviation cell is the first input terminal of the cascading module, the second input terminal of the first deviation cell is the second input terminal of the cascading module, the first output terminal of the k th deviation cell is connected to the first input terminal of the (k+1) th deviation cell, the second output terminal of the k th deviation cell is connected to the second input terminal of the (k+1) th deviation cell, k=1, 2, . . . , n−1, the first output terminal of the nth deviation cell is the first output terminal of the cascading module, and the second output terminal of the nth deviation cell is the second output terminal of the cascading module.
8 . A strong PUF circuit capable of implementing multi-bit parallel XOR operations according to claim 7 , wherein each deviation cell comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a fourth inverter, wherein an input terminal of the fourth inverter, a gate of the third NMOS transistor and a gate of the sixth NMOS transistor are connected and a connecting terminal is the signal input terminal of the deviation cell, a drain of the third NMOS transistor and a drain of the fourth NMOS transistor are connected and a connecting terminal is the first input terminal of the deviation cell, a drain of the fifth NMOS transistor and a drain of the sixth NMOS transistor are connected and a connecting terminal is the second input terminal of the deviation cell, a gate of the fourth NMOS transistor, a gate of the fifth NMOS transistor and an output terminal of the fourth inverter are connected, a source of the third NMOS transistor and a source of the fifth NMOS transistor are connected and a connecting terminal is the first output terminal of the deviation cell, and a source of the fourth NMOS transistor and a source of the sixth NMOS transistor are connected and a connecting terminal is the second output terminal of the deviation cell.
9 . A strong PUF circuit capable of implementing multi-bit parallel XOR operations according to claim 3 , wherein the control module comprises a first two-input AND gate, a second two-input AND gate, a seventh NMOS transistor and an eighth NMOS transistor, wherein the first two-input AND gate and the second two-input AND gate each have a first input terminal, a second input terminal and an output terminal, the first input terminal of the first two-input AND gate is the first control terminal of the control module, the first input terminal of the second two-input AND gate is the second control terminal of the control module, the second input terminal of the first two-input AND gate and the second input terminal of the second two-input AND gate are connected and a connecting terminal is the pre-charge terminal of the control module, a drain of the seventh NMOS transistor is the first input terminal of the control module, a drain of the eighth NMOS transistor is the second input terminal of the control module, a source of the seventh NMOS transistor and a source of the eighth NMOS transistor are connected and a connecting terminal is the ground terminal of the control module, a gate of the seventh NMOS transistor and the output terminal of the first two-input AND gate are connected, and a gate of the eighth NMOS transistor and the output terminal of the second two-input AND gate are connected.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the priority benefit of China application serial no. 202410768740.3, filed on Jun. 14, 2024. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. BACKGROUND Technical Field The invention relates to PUF circuits, in particular to a strong PUF circuit capable of implementing multi-bit parallel XOR operations. Description of Related Art At present, the study related to edge artificial intelligence (AI) is a focus in academia and industry and is an important category in numerous AI and IoT infrastructure chips. The large-scale application of edge AI chips to terminals allows for the deployment of AI algorithms and models on edge devices near a data source to perform calculation and inference. However, the calculation, storage and power of IoT chips represented by such edge AI chips are seriously limited, and data are generally processed on devices locally, leading to the risk of data leakage and security vulnerabilities and the requirement for extra security measures to protect the pravity and sensitive information of users. However, due to the limitation inn resources, it is difficult to deploy traditional classical encryption/decryption algorithms on these chips. The physically unclonable function (PUF), as a chip fingerprint technique, can generate random, unique and tamper-proof chip feature keys by extracting random process deviations which are inevitably introduced during the chip fabrication process. The PUF technique can overcome the limitation in the deployment of traditional classical encryption/decryption algorithms on these chips. At present, PUF circuits have been added to edge AI chips to improve the security of the edge AI chips. However, the direct addition of the PUF circuits will inevitably increase the hardware resource consumption of the edge AI chips and reduce the calculation efficiency of the edge AI chips, thus affecting the deployment of the edge AI chips in edge nodes. A common method used for improving the calculation efficiency of edge AI chips is to replace a complex multiply-accumulate operation with an XOR/XNOR logic algorithm, that is, by an XOR operation circuit in the edge AI chips. If the PUF circuit can be endowed with the XOR operation function to eliminate the XOR operation circuit, the PUF circuit and the XOR operation circuit will occupy a smaller area of the edge AI chips, thus reducing the area of the edge AI chips. This is of great significance for reducing the hardware resource consumption of the edge AI chips and improving the calculation efficiency of the edge AI chips. SUMMARY The technical issue to be settled by the invention is to provide a strong PUF circuit capable of implementing multi-bit parallel XOR operations, which can replace a separated PUF circuit and an XOR operation circuit to be applied to edge AI chips so as to reduce the area and hardware resource consumption of the edge AI chips and improve the calculation efficiency of the edge AI chips. The technical solution adopted by the invention to settle the above technical issue is as follows: a strong PUF circuit capable of implementing multi-bit parallel XOR operations comprises a presetting module, an interleaving module, a cascading module and a control module, wherein the control module is used for controlling an operating mode of the strong PUF circuit capable of implementing multi-bit parallel XOR operations, and under the control of the control module, the strong PUF circuit capable of implementing multi-bit parallel XOR operations is able to operate in a PUF mode, a logic operation mode or a power control mode; in a case where the strong PUF circuit capable of implementing multi-bit parallel XOR operations operates in the PUF mode, the cascading module is used for controlling the presetting module to generate two reverse response values, and the interleaving module is used for alternately selecting the two response values generated by the presetting module as PUF response outputs of the strong PUF circuit capable of implementing multi-bit parallel XOR operations; in a case where the strong PUF circuit capable of implementing multi-bit parallel XOR operations operates in the logic operation mode, the cascading module is used for inputting XOR operation data, controlling the presetting module to generate an XOR operation result and an XNOR operation result and outputting the XOR operation result and the XNOR operation result; and in a case where the strong PUF circuit capable of implementing multi-bit parallel XOR operations operates in the power control mode, low-power operation of the strong PUF circuit capable of implementing multi-bit parallel XOR operations is realized. In the case where the strong PUF circuit capable of implementing multi-bit parallel XOR operations operates in the PUF mode, the presetting module is able to improve the stability o