US-12627298-B2 - Circuitry and a method for generating a set of output clock signals

US12627298B2US 12627298 B2US12627298 B2US 12627298B2US-12627298-B2

Abstract

A circuitry for generating output clock signals with increasing phase delays comprises: an input receiving input clock signals with increasing phase delays, wherein the output clock signals are twice as many as the input clock signals; logic components connected in a loop with an output from a component connected as a first input to a following component, wherein the output is further connected as a second input to an oppositely positioned component; wherein each component receives the first, the second and a third input signal; wherein pairs of oppositely positioned components receive a common input clock signal and mask out the third input clock signal based on logic state of first and second input signals such that the outputs are phase shifted by 180 degrees; and wherein the circuitry outputs the output clock signals based on outputs from each component.

Inventors

SHUN NAGATA
Ewout Martens
Jan Craninckx

Assignees

IMEC VZW

Dates

Publication Date: 20260512
Application Date: 20240219
Priority Date: 20230220

Claims (5)

1 . A circuitry for generating a set of output clock signals defining a plurality of output clock signals with increasing phase delays, said circuitry comprising: an input configured to receive a set of input clock signals defining a plurality of input clock signals with increasing phase delays, wherein a number of the plurality of output clock signals is twice as large as a number of input clock signals; a plurality of logic components, wherein a number of the plurality of logic components is twice as large as a number of input clock signals, wherein the plurality of logic components is connected in a loop such that an output from each respective logic component of the plurality of logic components is connected as a first input to a respective following logic component of the plurality of logic components in the loop, wherein the output of each respective logic component is further connected as a second input to a respective logic component oppositely positioned in the loop, wherein each of the plurality of logic components is formed by a NOR logic gate or a NAND logic gate being a single logic gate of the logic component; wherein each logic component is configured to receive a first input signal at the first input, a second input signal at the second input, and a third input signal and provide the output, wherein the third input signal is an input clock signal of the plurality of input clock signals; wherein pairs of logic components oppositely positioned in the loop are configured to receive a common input clock signal of the plurality of input clock signals and different pairs of logic components oppositely positioned in the loop are configured to receive different input clock signals of the plurality of input clock signals and wherein logic components arranged in a sequence in the loop are configured to receive different input clock signals in a sequence defining increasing phase delay, wherein for each pair of logic components the oppositely positioned logic components are configured to mask out the third input signal based on logic state of the first input and the second input such that the outputs of the oppositely positioned logic components are phase shifted by 180 degrees with respect to each other; and wherein the circuitry is configured to output the set of output clock signals based on outputs from each logic component.
2 . The circuitry according to claim 1 , wherein the circuitry is configured to receive a four-phase quadrature input clock signal that forms the set of input clock signals and to output an 8-phase clock signal as the set of output clock signals.
3 . The circuitry according to claim 1 , wherein the circuitry is configured to receive the input clock signal having a duty cycle of a state to be masked out by the logic components of at least 25%.
4 . The circuitry according to claim 1 , wherein the output clock signals are formed by a multi-phase clock signal, and the circuitry is configured to output the multi-phase clock signal with an overlap between pulses of sequential phases in the multi-phase clock signal.
5 . The circuitry according to claim 1 , wherein the output clock signals are formed by a multi-phase clock signal, and a frequency of the multi-phase clock signal is half of a frequency of the input clock signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims the benefit of and priority to EP Patent Application Serial No. 23157525.9, filed Feb. 20, 2023, the entire contents of which is incorporated herein by reference. TECHNICAL FIELD The present description relates to a circuitry and a method for generating a set of output clock signals. BACKGROUND In some applications, a set of clock signals defining a plurality of clock signals with increasing phase delays, which may also be referred to as a multi-phase clock signal, are used. The plurality of clock signals provides pulses with different timing which may be used for providing different clock signals to different components in a circuit. For instance, having a large number of clock signals, such as 8, may be required for a high-speed time-interleaved analog-to-digital converter (ADC) or a phased array system. There are available architectures for 4-phase clock signal generators, such as using a frequency divider generating 4-phase clock signals from a differential input clock signal. However, there are difficulties when generating a larger set of clock signals is needed, such as an 8-phase clock signal. For instance, an 8-phase clock signal generator can be realized by one or more phase interpolator circuits, optionally in combination with 4-phase clock generators. However, the phase interpolator circuit needs calibration to obtain a good phase accuracy between 8 phases which also needs to track, e.g., temperature variations. The phase interpolator circuit may thus include a programmable delay line which limits the input frequency of the clock generator to a narrow frequency range. In WO 2022/133988, a multi-phase clock generation circuit is disclosed. The multi-phase clock generation circuit is used for generating multi-phase non-overlapping clock signals. The multi-phase clock generation circuit comprises a loop structure formed by the input ends and output ends of a plurality of logic gates being electrically connected end to end, and a plurality of latches used for lathing the signals of the input ends of the logic gates. However, use of logic gates as well as latches reduces robustness of the circuit, maximum frequency of operation, and there is also a risk of phase swapping occurring, i.e., that order of phases output by the plurality of logic gates is changed. SUMMARY An objective of the present description is to provide a circuitry and method for generating a set of output clock signals with increasing phase delays, wherein a robust and reliable generation of clock signals at high speed is provided. This and other objectives are at least partly met by the invention as defined in the independent claims. Preferred embodiments are set out in the dependent claims. According to a first aspect, there is provided a circuitry for generating a set of output clock signals defining a plurality of output clock signals with increasing phase delays, said circuitry comprising: an input configured to receive a set of input clock signals defining a plurality of input clock signals with increasing phase delays, wherein a number of the plurality of output clock signals is twice as large as a number of input clock signals; a plurality of logic components, wherein a number of the plurality of logic components is twice as large as a number of input clock signals, wherein the plurality of logic components is connected in a loop such that an output from each respective logic component of the plurality of logic components is connected as a first input to a respective following logic component of the plurality of logic components in the loop, wherein the output of each respective logic component is further connected as a second input to a respective logic component oppositely positioned in the loop; wherein each logic component is configured to receive the first, the second and a third input signal and provide the output, wherein the third input signal is an input clock signal of the plurality of input clock signals; wherein pairs of logic components oppositely positioned in the loop are configured to receive a common input clock signal of the plurality of input clock signals and different pairs of logic components oppositely positioned in the loop are configured to receive different input clock signals of the plurality of input clock signals and wherein logic components arranged in a sequence in the loop are configured to receive different input clock signals in a sequence defining increasing phase delay, wherein for each pair of logic components the oppositely positioned logic components are configured to mask out the third input clock signal based on logic state of first and second input signals such that the outputs of the oppositely positioned logic components are phase shifted by 180 degrees with respect to each other; and wherein the circuitry is configured to output the set of output clock signals based on outputs from each logic component. The circu