US-12627299-B2 - Controlling and powering multiple chips

Abstract

An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

Inventors

• Shahriar Ilislamoo
• David Carlson
• Barun Kar
• Darshan Shah

Assignees

• Auradine, Inc.

Dates

Publication Date

20260512

Application Date

20250618

Claims (20)

1. 1 . An electronic circuit, comprising: an event detector circuit; and a plurality of integrated circuit (IC) chips that are configured to respectively provide a plurality of output signals to the event detector circuit in parallel with one another, wherein the event detector circuit is configured to: receive the plurality of output signals from the plurality of IC chips, generate a data output signal that indicates toggling of a first output signal of the plurality of output signals, and transmit the data output signal to a computing device.
2. 2 . The electronic circuit of claim 1 , wherein the event detector circuit is configured to configured to generate the data output signal such that the data output signal toggles in response to the toggling of the first output signal.
3. 3 . The electronic circuit of claim 1 , wherein the event detector circuit is configured to generate the data output signal such that the data output signal is static in response to static output signals of the plurality of output signals.
4. 4 . The electronic circuit of claim 1 , wherein the event detector circuit comprises an XOR logic element configured to: perform a combined XOR operation on the plurality of output signals; and transmit, as the data output signal, an output of the combined XOR operation to the computing device.
5. 5 . The electronic circuit of claim 1 , wherein the event detector circuit is configured to detect whether the plurality of output signals include data or are static.
6. 6 . The electronic circuit of claim 1 , wherein the event detector circuit is configured to generate the data output signal such that the data output signal indicates changes in the plurality of output signals.
7. 7 . The electronic circuit of claim 6 , wherein the event detector circuit is configured to generate the data output signal such that the data output signal indicates bit-to-bit changes in the plurality of output signals.
8. 8 . The electronic circuit of claim 1 , wherein the event detector circuit is configured to generate the data output signal such that a presence of bit-to-bit changes in the data output signal is independent of a presence and polarity of any static output signals of the plurality of output signals.
9. 9 . An electronic circuit, comprising: a plurality of integrated circuit (IC) chips that are configured to perform computations in parallel; and an event detector logic circuit that is electrically coupled to the plurality of IC chips and configured to: receive, from the plurality of IC chips, a plurality of output signals that are based on respective computations by the plurality of IC chips; generate a data output signal that includes data obtained from a first output signal of the plurality of output signals; and transmit the data output signal to a computing device.
10. 10 . The electronic circuit of claim 9 , wherein the plurality of IC chips are configured to perform a same type of computation in parallel.
11. 11 . The electronic circuit of claim 10 , wherein the same type of computation comprises hash computations.
12. 12 . The electronic circuit of claim 9 , wherein each IC chip of the plurality of IC chips is configured to, in response to determining that the computations performed by the IC chip satisfy an objective: automatically generate the output signal corresponding to the IC chip such that the output signal includes a result of the computations performed by the IC chip; and automatically forward the output signal corresponding to the IC chip to the computing device.
13. 13 . The electronic circuit of claim 9 , wherein each IC chip of the plurality of IC chips is configured such that: the output signal corresponding to the IC chip toggles based on the IC chip outputting a result of the computations, and the output signal corresponding to the IC chip is static when the IC chip is not outputting a result of the computations.
14. 14 . The electronic circuit of claim 9 , wherein each IC chip of the plurality of IC chips is configured to, without receiving a corresponding poll command, generate and forward the output signal corresponding to the IC chip such that the output signal includes a result of the computations performed by the IC chip.
15. 15 . An electronic circuit, comprising: a plurality of integrated circuit (IC) chips on a common circuit board, wherein the plurality of IC chips are electrically connected in parallel to at least one control bus configured to provide input signals, and wherein the plurality of IC chips comprise respective power inputs configured to receive a supply voltage from a power supply; and a plurality of isolation resistors electrically connected between at least one of: (i) a signal input of each of the plurality of IC chips and the at least one control bus, or (ii) the power input of each of the plurality of IC chips and the power supply.
16. 16 . The electronic circuit of claim 15 , wherein the plurality of isolation resistors are electrically connected between the signal input of each of the plurality of IC chips and the at least one control bus, and wherein the plurality of isolation resistors have resistance values such that a total resistance value between the signal input of each of the plurality of IC chips and the at least one control bus is in a range from 100Ω to 1 kΩ.
17. 17 . The electronic circuit of claim 15 , wherein the plurality of isolation resistors are electrically connected between the signal input of each of the plurality of IC chips and the at least one control bus, and wherein the plurality of IC chips are configured to receive command signals, at the signal inputs of the plurality of IC chips, having speeds less than 50 MHz.
18. 18 . The electronic circuit of claim 15 , wherein the plurality of isolation resistors are electrically connected between the power input of each of the plurality of IC chips and the power supply, and wherein the plurality of isolation resistors have resistances sufficiently large that, in response to a power short at a first IC chip of the plurality of IC chips, a short current through the first IC chip is less than a maximum current corresponding to the power supply.
19. 19 . The electronic circuit of claim 15 , wherein the plurality of isolation resistors are electrically connected between the power input of each of the plurality of IC chips and the power supply, and wherein the plurality of isolation resistors have resistances sufficiently small that a voltage drop across a first isolation resistor, electrically connected between the power supply and a first IC chip of the plurality of IC chips, is less than 10% of a voltage supplied by the power supply.
20. 20 . The electronic circuit of claim 15 , wherein the plurality of isolation resistors are electrically connected between the power input of each of the plurality of IC chips and the power supply, and wherein the plurality of isolation resistors have resistance values such that a total resistance value between the power input of each of the plurality of IC chips and the power supply is in a range from 1Ω to 20Ω.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation application of U.S. patent application Ser. No. 19/035,308, filed on Jan. 23, 2025, which claims the benefit of the filing date of U.S. Provisional Patent Application No. 63/568,375, filed on Mar. 21, 2024, the entirety of each of these applications being incorporated herein by reference. FIELD OF THE DISCLOSURE This specification generally relates to signal processing and power control and, more specifically, to methods, integrated circuit (IC) chips, and electronic circuits related to processing and transmitting signals for multiple chips. BACKGROUND An electronic circuit can include multiple IC chips. Each of the IC chips can generate signals indicative of computations performed by the IC chips. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A-1B are diagrams illustrating an example of an electronic circuit. FIGS. 2A-2B are diagrams illustrating examples of integrated circuit (IC) chips. FIG. 3 is a diagram illustrating an example of signal processing. FIG. 4 is a diagram illustrating an example of a computer system. SUMMARY The aspects of the present disclosure relate to an electronic circuit. The electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus providing input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals. This and other electronic circuits described herein can have one or more of at least the following characteristics. In some implementations, the data output signal is generated such that the data is included in the data output signal insensitively to a presence and polarity of any static output signals of the plurality of output signals, and transmit the data output signal to the computing device In some implementations, the event detector logic circuit includes an XOR logic element configured to: perform a combined XOR operation on the plurality of output signals; and transmit, as the data output signal, an output of the combined XOR operation to the computing device. In some implementations, the event detector logic circuit is configured to detect whether the plurality of output signals include data or are static. In some implementations, the event detector logic circuit is configured to generate the data output signal such that the data output signal indicates changes in the plurality of output signals. In some implementations, the event detector logic circuit is configured to generate the data output signal such that the data output signal indicates bit-to-bit changes in the plurality of output signals. In some implementations, the event detector logic circuit is configured to generate the data output signal such that a presence of bit-to-bit changes in the data output signal is independent of the presence and polarity of any static output signals of the plurality of output signals. In some implementations, the event detector logic circuit is configured to generate the data output signal such that a polarity of the data output signal is based on the presence and polarity of any static output signals of the plurality of output signals. In some implementations, the data in the data output signal is encoded as a plurality of bits. The event detector logic circuit is configured to generate the data output signal such that a polarity of the plurality of bits is based on the presence and polarity of any static output signals of the plurality of output signals. In some implementations, the computing device is configured to: determine a polarity of the data output signal. In some implementations, the computing device is configured to extract the data from the data output signal based on the determined polarity of the data output signal. In some implementations, the electronic circuit includes a plurality of isolation resistors electrically connected between a signal input of each of the plurality of IC chips and the at least one control bus. In some implementations, the electronic circuit includes: a power supply configured to provide a supply voltage to a power input of each of the plurality of IC chips; and a plurality of isolation resistors electrically connected between the power input of each of the plurality of IC chips and the power supply. In some implementations, the computing device is configured to identify a predetermined non-static signal in the data output signal. In some implementations, an IC chip of the plurality of IC chips includes at least one processor unit configured to perform one or more mathematical computations, and the IC chip is configured to generate an output signal based on the one or more mathematical computations