US-12627301-B2 - Clock generation device and clock generation method using the same

US12627301B2US 12627301 B2US12627301 B2US 12627301B2US-12627301-B2

Abstract

A clock generation device includes a delay line that generates a modulated clock signal from a reference clock signal having a first period, a pulse generator configured to receive the modulated clock signal and generate a pulse signal in response to edges of pulses included in the modulated clock signal, and a clock generator that generates a clock signal having a second period distinguished from the first period, based on the reference clock signal and the pulse signal. The delay line generates a first pulse based on the reference clock signal and then generates a second pulse after a time modulated from the first period by a result of multiplying the second period by a first numerical value selected from a plurality of numerical values according to a certain probability.

Inventors

Baekmin LIM
GYUSIK KIM
Seungjin Kim
Seunghyun Oh

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20240402
Priority Date: 20230405

Claims (20)

1 . A clock generation device comprising: a delay line configured to generate a modulated clock signal from a reference clock signal having a first period; a pulse generator configured to receive the modulated clock signal and to generate a pulse signal in response to edges of pulses included in the modulated clock signal; and a clock generator configured to generate a clock signal having a second period distinguished from the first period, based on the reference clock signal and the pulse signal, wherein the delay line generates a first pulse, and subsequently a second pulse, based on the reference clock signal, wherein a time difference between generation of the first pulse and the second pulse is based on a value obtained by multiplying the second period by a first numerical value, and wherein the first numerical value is selected from a plurality of numeral values according to a certain probability.
2 . The clock generation device of claim 1 , wherein the clock generator comprises: a phase detector configured to detect a phase difference between the reference clock signal and a divided clock signal obtained by dividing the clock signal; a loop filter configured to generate a control signal, based on the phase difference; and an oscillator configured to output the clock signal having the second period based on the control signal and the pulse signal.
3 . The clock generation device of claim 2 , further comprising: a divider configured to divide the clock signal; and a delta sigma modulator connected to the divider, wherein the divider divides the clock signal with a fractional value, based on dividing ratio information generated by the delta sigma modulator, wherein the phase detector determines a phase difference between the divided clock signal divided with the fractional value and the reference clock signal, and wherein the dividing ratio information includes a ratio of a frequency of the reference clock signal and a frequency of the clock signal.
4 . The clock generation device of claim 1 , wherein the clock generator generates the clock signal including pulses each synchronized with the reference clock signal at a point in time when a pulse included in the pulse signal is received.
5 . The clock generation device of claim 1 , wherein the delay line comprises a selector configured to select the first numerical value, and wherein the selector selects the first numerical value determined according to the certain probability based on a pseudo random binary sequence (PRBS) pattern allowing each of the plurality of numerical values to be selected with the certain probability.
6 . The clock generation device of claim 5 , wherein the delay line further comprises: a plurality of modulation circuits each outputting a signal modulated by the second period from an input signal, and wherein the delay line outputs the modulated clock signal output through a number of the modulation circuits which corresponds to the first numerical value, from among the plurality of modulation circuits, based on a selection signal that corresponds to the first numerical value.
7 . The clock generation device of claim 6 , wherein the delay line further comprises a reference circuit, wherein the reference circuit receives the clock signal and outputs a modulation signal allowing a signal modulated by the second period from the clock signal to be output, and wherein each of the plurality of modulation circuits delays an input signal by the second period, based on the modulation signal.
8 . The clock generation device of claim 7 , wherein the reference circuit outputs the modulation signal, which allows each of the plurality of modulation circuits to modulate an input signal by the second period, based on a phase difference between the signal modulated by the second period from the clock signal and the clock signal.
9 . The clock generation device of claim 5 , wherein the delay line generates a third pulse after a time, which is obtained by modulating the first period by a multiplication value of the second period and a second numerical value distinguished from the first numerical value, from a point in time when the second pulse is generated, and wherein the second numerical value is determined depending on the certain probability based on the PRBS pattern.
10 . The clock generation device of claim 9 , wherein the first pulse, the second pulse, and the third pulse cause spurious components below a preset threshold value at different frequencies, respectively, together with the clock signal.
11 . A clock generation method comprising: receiving a reference clock signal having a first period; generating a modulated clock signal based on the reference clock signal; generating a pulse signal in response to edges of a plurality of pulses included in the modulated clock signal; and generating a clock signal having a second period distinguished from the first period, based on the pulse signal and the reference clock signal, wherein the generating of the modulated clock signal comprises: generating a first pulse based on the reference clock signal; and after generating the first pulse, generating a second pulse after a time based on a value obtained by multiplying the second period by a first numerical value, and wherein the first numerical value is selected from a plurality of numerical values according to a certain probability.
12 . The clock generation method of claim 11 , wherein the generating of the clock signal based on the pulse signal and the reference clock signal comprises: determining, by a phase detector, a phase difference between the reference clock signal and a divided clock signal obtained by dividing the clock signal; generating a control signal based on the determined phase difference; and outputting, by an oscillator, the clock signal having the second period based on the control signal and the pulse signal.
13 . The clock generation method of claim 11 , wherein the clock signal includes pulses synchronized with the reference clock signal at points in time when the first pulse and the second pulse are respectively generated.
14 . The clock generation method of claim 11 , further comprising: outputting a selection signal based on the first numerical value, based on a pseudo random binary sequence (PRBS) pattern allowing each of the numerical values to be selected with the certain probability.
15 . The clock generation method of claim 11 , wherein at least two or more pulses of the pulse signal cause spurious components below a preset threshold value at different frequencies, respectively, together with the clock signal.
16 . A clock generation device comprising: a delay line configured to generate a modulated clock signal from a reference clock signal having a first period; a pulse generator connected to the delay line, and configured to generate a pulse signal in response to edges of a plurality of pulses included in the modulated clock signal; a phase detector configured to detect a phase difference between the reference clock signal and a divided clock signal; a loop filter configured to generate a control signal, based on the phase difference from the phase detector; and an oscillator configured to output a clock signal having a second period based on the control signal and the pulse signal, wherein the delay line generates a first pulse based on the reference clock signal, and a second pulse following the first pulse by a time based on a value obtained by multiplying the second period by a first numerical value, and wherein the first numerical value is selected from a plurality of numerical values according to a certain probability.
17 . The clock generation device of claim 16 , wherein the first numerical value is selected based on a pseudo random binary sequence (PRBS) pattern allowing each of the plurality of numerical value to be selected with the certain probability.
18 . The clock generation device of claim 17 , wherein the delay line generates a third pulse after a time, which is obtained by modulating the first period by a multiplication value of the second period and a second numerical value distinguished from the first numerical value, from a point in time when the second pulse is generated, and wherein the second numerical value is determined from the plurality of numerical values depending on the certain probability, based on the PRBS pattern.
19 . The clock generation device of claim 18 , wherein the first pulse, the second pulse and the third pulse cause spurious components below a preset threshold value at different frequencies, respectively, together with the clock signal.
20 . The clock generation device of claim 16 , wherein the oscillator outputs the clock signal including pulses each synchronized with the reference clock signal at a point in time when the pulse signal is received.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application Nos. 10-2023-0044975 filed on Apr. 5, 2023, and 10-2023-0125653 filed on Sep. 20, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference in their entireties herein. 1. Technical Field Embodiments of the present disclosure described herein are directed to a clock generation device and a clock generation method using the same. 2. Discussion of Related Art An operation of an integrated circuit which processes digital signals may be synchronized with a clock signal. The integrated circuit may also use the clock signal to process an analog signal such as a signal in a radio frequency (RF) frequency band. For example, data may be transmitted or received in synchronization with the clock signal like the data communication between a memory device and a memory controller. As the load of a bus transferring the data increases and a frequency of transferring the data becomes higher, the timing to synchronize the clock signal and the data becomes more important. A phase-locked loop (PLL) or a delay-locked loop (DLL) may be used to synchronize the clock signal and the data. The phase-locked loop and the delay-locked loop are used in various application circuits to maintain the clock signal. However, these circuits may generate the clock signal with spurious components that make it difficult to synchronize the clock signal and the data. SUMMARY At least one embodiment of the present disclosure provides a clock generation device that increases the quality of a clock signal generated from a reference clock signal. According to an embodiment, a clock generation device includes a delay line, a pulse generator and clock generator. The delay line generates a modulated clock signal from a reference clock signal having a first period. The pulse generator is configured to receive the modulated signal and generate a pulse signal in response to edges of pulses included in the modulated clock signal. The clock generator generates a clock signal having a second period distinguished from the first period, based on the reference clock signal and the pulse signal. The delay line generates a first pulse based on the reference clock signal and then generates a second pulse after a time modulated from the first period by a result of multiplying the second period by a first numerical value selected from a plurality of numerical values according to a certain probability. According to an embodiment, a clock generation method includes: receiving a reference clock signal having a first period; generating a modulated clock signal based on the reference clock signal; generating a pulse signal in response to edges of a plurality of pulses included in the modulated clock signal; and generating a clock signal having a second period distinguished from the first period, based on the pulse signal and the reference clock signal. The generating of the modulated clock signal includes: generating a first pulse based on the reference clock signal; and generating a second pulse after a time obtained by modulating the first period by a result of multiplying the second period by a first numerical value, after generating the first pulse. The first numerical value may be selected from a plurality of numerical values according to a certain probability. According to an embodiment, a clock generation device includes a delay line, a pulse generator, a phase detector, a loop filter, and an oscillator. The delay line generates a modulated clock signal from a reference clock signal having a first period. The pulse generator is connected to the delay line and generates a pulse signal in response to edges of a plurality pulses included in the modulated clock signal. The phase detector detects a phase difference between the reference clock signal and a divided clock signal. The loop filter generates a control signal, based on the phase difference from the phase detector. The oscillator outputs a clock signal having a second period based on the control signal and the pulse signal. The delay line generates a second pulse after a time obtained by modulating the first period by a result of multiplying the second period by a first numerical value, from a point in time when a first pulse is generated based on the reference clock signal. The first numerical value is selected from a plurality of numerical values according to a certain probability. BRIEF DESCRIPTION OF THE FIGURES The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments thereof with reference to the accompanying drawings. FIG. 1 is a block diagram illustrating a clock generation device according to an embodiment of the present disclosure. FIG. 2A is a block diagram illustrating a clock generation device according to an embodiment. FIG. 2B illustrates a pulse signal and a