US-12627302-B2 - Delay line temperature calibration

US12627302B2US 12627302 B2US12627302 B2US 12627302B2US-12627302-B2

Abstract

A delay-line circuit includes multiple variable-delay circuits and may generate an output signal that is a delayed version of an input signal. A calibration circuit includes an oscillator circuit that may generate an oscillator signal, and may include a replica of at least one of the multiple variable-delay circuits. The calibration circuit may perform an initial calibration of the delay-line circuit and, in response to a completion of the initial calibration, perform a background calibration of the delay-line circuit using the oscillator signal.

Inventors

Yudong Zhang
Hanan Cohen
Jacob S. Schneider
Sanjeev K. Maheshwari

Assignees

APPLE INC.

Dates

Publication Date: 20260512
Application Date: 20240506

Claims (20)

1 . An apparatus, comprising: a first delay-line circuit that includes a plurality of variable-delay circuits, wherein the first delay-line circuit is configured to generate at least one output signal using an input signal, and wherein the at least one output signal is a delayed version of the input signal; and a calibration circuit that includes an oscillator circuit configured to generate an oscillator signal, wherein the oscillator circuit includes a particular variable-delay circuit that is a replica of a given variable-delay circuit of the plurality of variable-delay circuits, wherein the calibration circuit is configured to: perform, as part of an initial calibration of the first delay-line circuit, a first phase-detection operation using the at least one output signal and the input signal; determine, as part of the initial calibration, a first control code using a first result of the first phase-detection operation; determine, as part of the initial calibration, a second control code using the first result of the first phase-detection operation; and perform, in response to a determination that the initial calibration has completed, a background calibration of the first delay-line circuit using the oscillator signal.
2 . The apparatus of claim 1 , wherein the calibration circuit is further configured to: adjust a first delay value of at least one variable-delay circuit of the plurality of variable-delay circuits using the first control code; and adjust a second delay value of the particular variable-delay circuit using the second control code.
3 . The apparatus of claim 1 , further comprising a second delay-line circuit configured to generate a global output signal using a global input signal, wherein the global output signal is a delayed version of the global input signal, and wherein the calibration circuit is further configured to: perform a second phase-detection operation using the global input signal and the global output signal; and determine the second control code using a second result of the second phase-detection operation.
4 . The apparatus of claim 1 , wherein to perform the background calibration, the calibration circuit is further configured to: perform a frequency detection operation on the oscillator signal; determine, using a result of the frequency detection operation, a first offset code and a second offset code; combine the first offset code with the first control code to generate a first combined code; combine the second offset code with the second control code to generate a second combined code; adjust a first delay value of at least one variable-delay circuit of the plurality of variable-delay circuits using the first combined code; and adjust a second delay value of the particular variable-delay circuit using the second combined code.
5 . The apparatus of claim 4 , wherein to perform the frequency detection operation, the calibration circuit is further configured to: generate a reduced-frequency signal using the oscillator signal, wherein a first frequency of the reduced-frequency signal is less than a second frequency of the oscillator signal; and determine a frequency of the reduced-frequency signal.
6 . The apparatus of claim 1 , wherein the calibration circuit is further configured to perform the background calibration at regular time intervals.
7 . A method, comprising: performing, by a calibration circuit that includes an oscillator circuit, an initial calibration of at least one delay line circuit that includes a plurality of variable-delay circuits, wherein the oscillator circuit includes a replica of at least one variable-delay circuit of the plurality of variable-delay circuits, and wherein the oscillator circuit is configured to generate at least one oscillator signal, wherein performing the initial calibration includes: generating, by the at least one delay circuit, an output signal using an input signal, wherein the output signal is a delayed version of the input signal; performing, by the calibration circuit, a first phase-detection operation using the input signal and the output signal; determining, by the calibration circuit using a result of the first phase-detection operation, a first control code for the at least one delay line circuit; determining, by the calibration circuit using the result of the first phase-detection operation, a second control code for the oscillator circuit included in the calibration circuit; and performing, by the calibration circuit in response to completing the initial calibration, a background calibration of the at least one delay line circuit using the at least one oscillator signal.
8 . The method of claim 7 , further comprising adjusting a delay value of a given variable-delay circuit of the plurality of variable-delay circuits using the first control code.
9 . The method of claim 7 , wherein determining the second control code includes: generating, by a different delay-line circuit, a global output signal using a global input signal, wherein the output signal is a delayed version of the input signal; performing, by the calibration circuit, a second phase-detection operation using the global input signal and the global output signal; and determining, by the calibration circuit using a result of the second phase-detection operation, the second control code.
10 . The method of claim 7 , wherein performing the background calibration includes: performing, by the calibration circuit, a frequency detection operation on an oscillator signal generated by the oscillator circuit; determining, by the calibration circuit using a result of the frequency detection operation, a first offset code and a second offset code; combining, by the calibration circuit, the first offset code with the first control code to generate a first combined code; combining, by the calibration circuit, the second offset code with the second control code to generate a second combined code; and adjusting a first variable-delay circuit in the at least one delay line circuit and a second variable-delay circuit in the oscillator circuit using the first combined code and the second combined code, respectively.
11 . The method of claim 10 , wherein performing the frequency detection operation includes: generating, by a frequency-divider circuit, a reduced-frequency signal using the oscillator signal; and determining, by a frequency-counter circuit, a frequency of the reduced-frequency signal.
12 . The method of claim 7 , further comprising performing, by the calibration circuit, the background calibration at periodic intervals.
13 . The method of claim 7 , wherein a periodicity of performing the background calibration is based on operation conditions of the calibration circuit.
14 . An apparatus, comprising: a first device coupled to a communication bus, wherein the first device is configured to transmit a first clock signal and data via the communication bus; and a second device coupled to the communication bus, wherein the second device includes a receiver circuit that includes: a first delay-line circuit that includes a plurality of variable-delay circuits, wherein the first delay-line circuit is configured to generate a delayed version of the first clock signal, and an oscillator circuit that includes a particular variable-delay circuit that is a replica of a given variable-delay circuit of the plurality of variable-delay circuits, wherein the oscillator circuit is configured to generate an oscillator signal; and wherein the second device is configured to: perform, as part of an initial calibration of the first delay-line circuit, a first phase-detection operation using the first clock signal and the delayed version of the first clock signal; determine, as part of the initial calibration of the first delay-line circuit, a first control code using a first result of the first phase-detection operation; determine, as part of the initial calibration of the first delay-line circuit, a second control code using the first result of the first phase-detection operation; perform, using the oscillator signal, a background calibration of the first delay-line circuit in response to a determination that the initial calibration has completed; and receive the data, via the communication bus, using the delayed version of the first clock signal.
15 . The apparatus of claim 14 , wherein the second device is further configured to: adjust a first delay value of at least one variable-delay circuit of the plurality of variable-delay circuits using the first control code; and adjust a second delay value of the particular variable-delay circuit using the second control code.
16 . The apparatus of claim 14 , wherein the first device is further configured to transmit a global clock signal via the communication bus, wherein the second device further includes a second delay-line circuit configured to generate a delayed global clock signal, wherein the delayed global clock signal is a delayed version of the global clock signal, and wherein to determine the second control code, the second device is further configured to: perform a second phase-detection operation using the global clock signal and the delayed global clock signal; and determine the second control code using a second result of the second phase-detection operation.
17 . The apparatus of claim 14 , wherein to perform the background calibration, the second device is further configured to: perform a frequency detection operation on the oscillator signal; determine, using a result of the frequency detection operation, a first offset code and a second offset code; combine the first offset code with the first control code to generate a first combined code; combine the second offset code with the second control code to generate a second combined code; adjust a first delay value of at least one variable-delay circuit of the plurality of variable-delay circuits using the first combined code; and adjust a second delay value of the particular variable-delay circuit using the second control code.
18 . The apparatus of claim 17 , wherein to perform the frequency detection operation, the second device is further configured to: generate a reduced-frequency signal using the oscillator signal, wherein a first frequency of the reduced-frequency signal is less than a second frequency of the oscillator signal; and determine a frequency of the reduced-frequency signal.
19 . The apparatus of claim 14 , wherein the second device is further configured to perform the background calibration at regular time intervals.
20 . The apparatus of claim 14 , wherein the second device is further configured to perform the background calibration based on operation conditions of the second device.

Description

FIELD The described embodiments relate generally to computer systems and, more particularly, to techniques for calibrating delay-line circuits used in the creation of delayed versions of signals. BACKGROUND Modern computer systems may include multiple circuit blocks designed to perform various functions. For example, such circuit blocks may include processors or processor cores configured to execute software or program instructions. Additionally, the circuit blocks may include memory circuits, mixed-signal circuits, analog circuits, and the like. Some computer systems include circuit blocks that include digital circuits that operate using a period digital signal referred to as a “clock signal.” Various circuits may be used to generate clock signals in a computer system. For example, in some computer systems, a crystal oscillator circuit or an inductor-capacitor oscillator circuit (referred to as an “LC oscillator circuit”) may be used to generate a clock signal that has a particular frequency. Clocks signals of other frequencies can be generated using phase-locked loop circuits or delay-locked loop circuits. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram depicting an embodiment of a delay-line subsystem. FIG. 2 is a block diagram depicting an embodiment of a delay-line circuit. FIG. 3 is a block diagram depicting an embodiment of a calibration circuit for a delay-line circuit. FIG. 4 is a block diagram depicting an embodiment of an oscillator circuit for a delay-line calibration circuit. FIG. 5A is a block diagram depicting an embodiment of a variable-delay circuit. FIG. 5B is a block diagram depicting an embodiment of a variable-delay stage used in a variable-delay circuit. FIG. 6 is a block diagram depicting an embodiment of an initial calibration circuit. FIG. 7 is a block diagram depicting an embodiment of a background calibration circuit. FIG. 8 is a block diagram depicting an embodiment of a computer system that transmits data between two devices. FIG. 9 is a flow diagram depicting an embodiment of a method for calibrating a delay-line circuit. FIG. 10 is a flow diagram depicting an embodiment of a method for performing an initial calibration operation of a delay-line circuit. FIG. 11 is a flow diagram depicting an embodiment of a method for performing a background calibration operation of a delay-line circuit. FIG. 12 is a block diagram of an embodiment of a device that includes delay-line subsystems. FIG. 13 is a block diagram of various embodiments of computer systems that may include delay-line subsystems. FIG. 14 illustrates an example of a non-transitory computer-readable storage medium that stores design information. DETAILED DESCRIPTION Computer systems may include multiple circuit blocks configured to use periodic signals, referred to as clock signals, to perform various operations. For example, in some computer systems, one or more clock signals may be used to send data from one device to another within the computer system. In such cases, the one or more clock signals may be transmitted along with the data, and the receiving device may use the one or more clock signals to sample the received data. A variety of techniques may be employed to generate the various clock signals a computer system may employ. In some cases, a crystal oscillator circuit or LC oscillator circuit may be used to generate a base clock signal that can be used to generate other clock signals of various frequencies. In some computer systems, phase-locked loop circuits or delay-locked loop circuits may be employed to generate the desired clock signals. Another technique for generating clock signals involves the use of a digitally controlled delay line (“DCDL”) circuit that generates different clocks signals with the same frequency but different phases by delaying an input clock signal by different time periods. For example, a DCDL circuit may be used to generate quadrature clock signals where the phase difference between each of the quadrature clock signals is 90-degrees. In some computer systems, quadrature clocks can be transmitted along with data from one device to another within the computer system. The receiving device can include a phase interpolator circuit that uses the phase difference between the quadrature clocks to determine when to sample the received data. Many DCDL circuits include both a fixed-delay path and a variable-delay path that generate respective clock signals by delaying an input clock signal. The delay of the variable-delay path can be adjusted to compensate for changes in the operating conditions of a computer system. For example, a change in temperature or power supply voltage can affect the delay of both the fixed-delay path and the variable-delay path. Control circuits can adjust the delay of the variable-delay path to maintain the desired phase difference between the generated clock signals. In some computer systems, variable-delay circuits included in DCDL circuits are adjusted