US-12627303-B1 - Synchronous time-to-charge converter

US12627303B1US 12627303 B1US12627303 B1US 12627303B1US-12627303-B1

Abstract

A time-to-charge converter (TCC) includes a phase detector configured to receive a first clock and a second clock and output a phase error signal indicative of the time difference between the second clock and the first clock; a current source configured to generate a tail current; a current directing network configured to direct the tail current towards either a first node or a second node based on the phase error signal; a synchronous clock generator configured to receive the first clock and generate a third clock that is synchronous to the first clock but has an independently determined duty cycle; an integration capacitor having a top plate connected to the second node and a bottom plate driven by an inversion of the third clock; a switch positioned between a third node and the second node, controlled by the third clock; and a load capacitor attached to the third node.

Inventors

Chia-Liang (Leon) Lin

Assignees

REALTEK SEMICONDUCTOR CORP.

Dates

Publication Date: 20260512
Application Date: 20241108

Claims (9)

1 . A TCC (time-to-charge converter) comprising: a phase detector configured to receive a first clock and a second clock and output a phase error signal indicative of a time difference between the second clock and the first clock; a current source configured to generate a tail current; a current directing network configured to direct the tail current towards either a first node or a second node based on the phase error signal; a synchronous clock generator configured to receive the first clock and generate a third clock that is synchronous to the first clock but has an independently determined duty cycle; an integration capacitor having a top plate connected to the second node and a bottom plate driven by an inversion of the third clock; a switch positioned between a third node and the second node and controlled by the third clock; and a load capacitor attached to the third node.
2 . The TCC of claim 1 , wherein the first clock is a reference clock that has a stable periodic timing.
3 . The TCC of claim 2 , wherein the first clock is generated by a crystal oscillator.
4 . The TCC of claim 1 , wherein the phase error signal has a rising edge in response to a rising edge of the second clock and a falling edge in response to a rising edge of the first clock.
5 . The TCC of claim 4 , wherein the current directing network comprises a second switch controlled by the phase error signal and inserted between a junction node and the second node, and a first switch controlled by an inversion of the phase error signal and inserted between the junction node and the first node, wherein the junction node attaches to the current source.
6 . The TCC of claim 1 , further comprising a low-impedance active load attached to the first node and comprising a MOS (metal oxide semiconductor) transistor with a source connected to the first node.
7 . The TCC of claim 1 , further comprising an offset charge transfer circuit comprising: a MOS (metal oxide semiconductor) transistor configured as a common-gate amplifier with a drain attached to the third node, a source connected to a source node through a source switch controlled by the third clock, and a gate controlled by a reference voltage; a source capacitor inserted between a power supply node and the source node; and a reset switch controlled by the inversion of the third clock and inserted between the power supply node and the source node.
8 . The TCC of claim 7 , further comprising a reference voltage generator comprising: a current source, a MOS transistor configured in a diode-connect topology with a drain connected to a gate and attached to the current source of the reference voltage generator and a source connected to the power supply node through a resistor, wherein the reference voltage is tapped at the gate of the MOS transistors of the reference voltage generator.
9 . The TCC of claim 1 further, wherein the synchronous clock generator comprises a delay circuit configured to receive the third clock and output a delayed clock, and a data flip-flop configured to output the third clock in accordance with the first clock and the delayed clock, wherein the first clock serves a trigger function, and the delayed clock serves a reset function.

Description

BACKGROUND OF THE INVENTION Field of the Invention The present invention generally relates to time-to-charge converter (TCC) and particularly to TCCs that are synchronous with a reference clock. Description of Related Art Those skilled in the art will understand and recognize the terms and fundamental concepts employed herein related to microelectronics, such as “voltage,” “current,” “signal,” “logical signal,” “clock,” “phase,” “(clock) edge,” “duty cycle,” “capacitor,” “transistor,” “node,” “ground node,” “power supply node,” “inverter,” “switch,” “common-gate amplifier,” “load,” “flip-flop,” “noise,” and “impedance.” The aforementioned terms and concepts, as utilized in the present disclosure, are readily comprehensible to those skilled in the art and thus do not require extensive elaboration. A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), hereinafter referred to as “MOS transistor” or “MOST,” is an active device comprising source, gate, and drain terminals, and is capable of operating as an amplifier or a switch. The MOST includes NMOS (n-channel) and PMOS (p-channel) transistors. The MOST remains in an off state and exhibits characteristics akin to an open circuit when the gate-to-source voltage is below a specified threshold voltage. The MOST enters an on state when the gate-to-source voltage surpasses the threshold voltage; in this scenario, it functions within the “saturation region” and operates effectively as an amplifier if the gate-to-drain voltage is below the threshold voltage. Conversely, it operates within the “linear region” and functions as a switch when the gate-to-drain voltage exceeds the threshold voltage. Those skilled in the art will recognize the symbols for a MOST, for both PMOS and NMOS transistors, and can identify a “source” terminal, a “gate” terminal, and a “drain” terminal of a MOST. For brevity, in the present disclosure, in the context of reference to a MOST, a “source terminal” is referred to as “source,” a “gate terminal” is referred to as “gate,” and a “drain terminal” is referred to as “drain.” Those skilled in the art will readily comprehend the connection between resistors, capacitors, MOS transistors, inverters, switches, and other components as depicted in circuit schematics. Therefore, a detailed description delineating the interconnections among these components is deemed unnecessary. A signal is either a voltage or current of a variable level that carries certain information and can vary with time. The level of the signal at a moment represents the state of the signal at that moment. A signal is a “voltage signal” (“current signal”) if it is a voltage (current). In this present disclosure, since “voltage signals” appear more often than “current signals,” for brevity a “signal” refers to a “voltage signal” unless it is otherwise specified as a “current signal.” A logical signal comprises two distinct states: low (0) and high (1). The expression “Q is high (1)” denotes that Q is in its high (1) state, whereas “Q is low (0)” indicates that Q is in its low (0) state. A logical signal can be utilized to either enable or disable a function; the state that effectuates the enablement of the function is herein referred to as the “on state.” Upon the transition of a logical signal from a low state (0) to a high state (1), or from a high state (1) to a low state (0), the occurrence of a rising edge or a falling edge is respectively observed. A pulse of the logical signal is thereby defined, commencing at the rising edge and concluding at the subsequent falling. A clock is a logical signal that cyclically toggles back and forth between 0 and 1. A duty cycle of a clock is a percentage of time that the clock remains 1. A time of a clock refers to a time instant at which a rising edge of the clock occurs. A time difference between a first clock and a second clock refers to the amount of separation between a time instant at which a rising edge of the first clock occurs and a time instant at which a rising edge of the second clock occurs. In the present disclosure, the terms “time” and “timing” as they pertain to a clock are synonymous and interchangeable, both referring to the time instant at which a rising edge occurs. In numerous applications, a time-to-charge converter is needed, wherein a time difference between a first clock and a second clock is detected and then converted into an electrical charge (hereafter charge for brevity) of amount proportional to the time difference. As shown in FIG. 1, a TCC (time-to-charge converter) 100 comprises: a PD (phase detector) 110 that detects a time difference between a first clock CK1 and a second clock CK2 and delivers a phase error signal that is jointly embodied by two logical signals UP and DN to represent the time difference; and a CP (charge pump) 120 that converts the phase error signal into a charge transferred to an output node 101, which is terminated with a load 130 that comprises a shunt capacitor 131 in par