US-12627305-B2 - Signal recovery system and storage device

US12627305B2US 12627305 B2US12627305 B2US 12627305B2US-12627305-B2

Abstract

A signal recovery system includes multiple frequency dividers, multiple signal recovery circuits, and a data signal generating circuit. The multiple frequency dividers perform a frequency dividing operation upon a clock signal and a data strobe signal, respectively, to generate a set of frequency-divided clock signals and a set of frequency-divided data strobe signals. The multiple signal recovery circuits perform a signal recovery operation upon the set of frequency-divided clock signals and the set of frequency-divided data strobe signals, respectively, to generate a recovered clock signal and a recovered data strobe signal. The data signal generating circuit generates a data signal according to the recovered clock signal and the recovered data strobe signal, for indicating whether a rising edge of the data strobe signal is located at a first level or a second level of the clock signal, wherein the first level is higher than the second level.

Inventors

Shu-Han Nien

Assignees

ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.

Dates

Publication Date: 20260512
Application Date: 20240409

Claims (15)

1 . A signal recovery system, comprising: multiple frequency dividers, arranged to perform a frequency dividing operation upon a clock signal and a data strobe signal, respectively, to generate a set of frequency-divided clock signals and a set of frequency-divided data strobe signals; multiple signal recovery circuits, arranged to perform a signal recovery operation upon the set of frequency-divided clock signals and the set of frequency-divided data strobe signals, respectively, to generate a recovered clock signal and a recovered data strobe signal; and a data signal generating circuit, arranged to generate a data signal according to the recovered clock signal and the recovered data strobe signal, for indicating whether a rising edge of the data strobe signal is located at a first level or a second level of the clock signal, wherein the first level is higher than the second level.
2 . The signal recovery system of claim 1 , wherein the set of frequency-divided clock signals comprises a first frequency-divided clock signal, a second frequency-divided clock signal, a third frequency-divided clock signal, and a fourth frequency-divided clock signal.
3 . The signal recovery system of claim 2 , wherein the first frequency-divided clock signal is generated according to a first rising edge of a corresponding signal before the frequency dividing operation the set of frequency-divided clock signals, the second frequency-divided clock signal is generated according to a first falling edge of the corresponding signal, the third frequency-divided clock signal is generated according to a second rising edge of the corresponding signal, and the fourth frequency-divided clock signal is generated according to a second falling edge of the corresponding signal.
4 . The signal recovery system of claim 3 , wherein the multiple signal recovery circuits are arranged to generate multiple recovery signals according to rising edges of the multiple frequency-divided clock signals.
5 . The signal recovery system of claim 4 , wherein the multiple recovery signals comprise a first recovery signal, a second recovery signal, a third recovery signal, and a fourth recovery signal.
6 . The signal recovery system of claim 5 , wherein the first recovery signal is generated according to rising edges of the first frequency-divided clock signal and the second frequency-divided clock signal; the second recovery signal is generated according to rising edges of the second frequency-divided clock signal and the third frequency-divided clock signal; the third recovery signal is generated according to rising edges of the third frequency-divided clock signal and the fourth frequency-divided clock signal; and the fourth recovery signal is generated according to rising edges of the first frequency-divided clock signal and the fourth frequency-divided clock signal.
7 . The signal recovery system of claim 6 , wherein one of the multiple signal recovery circuits comprises multiple logical combination circuits, and each of the multiple logical combination circuits corresponds to two of the frequency-divided clock signals, and comprises: a first NAND gate circuit, having a first input port for receiving the first frequency-divided clock signal through multiple first inverters, a second input port for receiving an inverted version of the second frequency-divided clock signal through at least one second inverter, and an output port, wherein one of the multiple recovery signals is generated according to the output port.
8 . The signal recovery system of claim 7 , wherein the one of the multiple recovery signals toggles from a third level to a fourth level in response to a rising edge of the first frequency-divided clock signal, and toggles from the fourth level to the third level in response to a rising edge of the second frequency-divided clock signal; and the third level is lower than the fourth level.
9 . The signal recovery system of claim 8 , wherein a number of the multiple first inverters is larger than a number of the at least one second inverter.
10 . The signal recovery system of claim 7 , wherein the one of the multiple signal recovery circuits further comprises: a first signal transmission circuit, arranged to determine whether to transmit a first voltage signal or a second voltage signal according to the first recovery signal and the second recovery signal, wherein a level of the first voltage signal is higher than a level of the second voltage signal; a second signal transmission circuit, arranged to determine whether to transmit the first voltage signal or the second voltage signal according to the third recovery signal and the fourth recovery signal; a second NAND gate circuit, having a first input port for receiving an output result of the first signal transmission circuit and a second input port for receiving an output result of the second signal transmission circuit; a third NAND gate circuit, having a first input port for receiving an output result of the second NAND gate circuit and a second input port for receiving the first voltage signal; and a third inverter, arranged to generate an inverted version of an output result of the third NAND gate circuit as the recovered clock signal.
11 . The signal recovery system of claim 10 , wherein the first signal transmission circuit comprises: a first transmission gate circuit, having an input port for receiving the first voltage signal, a control port for receiving the first recovery signal, and an output port; a second transmission gate circuit, having an input port for receiving the second voltage signal, a control port for receiving the second recovery signal, and an output port; and a fourth inverter, having a first terminal coupled to the output port of the first transmission gate circuit, the output port of the second transmission gate circuit, and a drain terminal of an N-type transistor, and a second terminal arranged to transmit an output result of the fourth inverter, wherein the N-type transistor determines whether to couple the first terminal of the fourth inverter to the second voltage signal according to a control signal.
12 . The signal recovery system of claim 11 , wherein the one of the multiple signal recovery circuits further comprises: a NOR gate circuit, having a first input port for receiving an inverted version of the output result of the first NAND gate circuit corresponding to the first recovery signal and a second input port for receiving an inverted version of the output result of the first NAND gate circuit corresponding to the second recovery signal, wherein an output result of the NOR gate circuit acts as the control signal.
13 . The signal recovery system of claim 10 , wherein the second signal transmission circuit comprises: a first transmission gate circuit, having an input port for receiving the first voltage signal, a control port for receiving the third recovery signal, and an output port; a second transmission gate circuit, having an input port for receiving the second voltage signal, a control port for receiving the fourth recovery signal, and an output port; and a fourth inverter, having a first terminal coupled to the output port of the first transmission gate circuit, the output port of the second transmission gate circuit, and a drain terminal of an N-type transistor, and a second terminal arranged to transmit an output result of the fourth inverter, wherein the N-type transistor determines whether to couple the first terminal of the fourth inverter to the second voltage signal according to a control signal.
14 . The signal recovery system of claim 13 , wherein the one of the multiple signal recovery circuits further comprises: a NOR gate circuit, having a first input port for receiving an inverted version of the output result of the first NAND gate circuit corresponding to the third recovery signal and a second input port for receiving an inverted version of the output result of the first NAND gate circuit corresponding to the fourth recovery signal, wherein an output result of the NOR gate circuit acts as the control signal.
15 . A storage device, comprising: a memory controller; a memory, comprising: multiple frequency dividers, arranged to receive a clock signal and a data strobe signal from the memory controller, and perform a frequency dividing operation upon the clock signal and the data strobe signal, respectively, to generate a set of frequency-divided clock signals and a set of frequency-divided data strobe signals; multiple signal recovery circuits, arranged to perform a signal recovery operation upon the set of frequency-divided clock signals and the set of frequency-divided data strobe signals, respectively, to generate a recovered clock signal and a recovered data strobe signal; and a data signal generating circuit, arranged to generate a data signal according to the recovered clock signal and the recovered data strobe signal, and transmit the data signal to the memory controller, for indicating whether a rising edge of the data strobe signal is located at a first level or a second level of the clock signal, wherein the first level is higher than the second level.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is related to a double data rate (DDR) synchronous dynamic random access memory (SDRAM), and more particularly, to a signal recovery system that can perform a write leveling operation by frequency division and signal recovery, and an associated storage device. 2. Description of the Prior Art With the development of the DDR SDRAM, frequency dividing operations are usually performed upon a clock signal with a high-speed frequency and a data strobe (DQS) signal to generate multiple frequency-divided signals clock and multiple frequency-divided DQS signals, for performing a data writing operation. For the LPDDR4, during a write leveling operation, the DDR SDRAM receives the clock signal and the DQS signal from a memory controller, and generate and transmit a data (DQ) signal back to the memory controller according to the clock signal and the DQS signal, for indicating whether a rising edge of the DQS signal is located at a high level or a low level of the clock signal. The memory controller may then determine whether to delay the DQS signal according to the DQ signal for successfully performing the data writing operation. For a conventional storage device including the memory controller and the DDR SDRAM, the clock signal and the DQS signal may be used to perform the write leveling operation through multiple delay circuits (e.g., multiple inverters) that imitate a delay of a normal data writing path. Some problems may occur, however. Under a condition that process, voltage, and temperature (PVT) varies, and the LPDDR4 specification only allows tDOSS to have a tolerance value of 1±0.25 tck (clock cycle time; i.e., at the fastest current clock speed, the clock cycle time tck is 0.46 nanoseconds (ns)), there may be a difference between a delay of the delay circuits and that of the normal data writing path, thereby causing errors in the subsequent data writing operation. As a result, a novel signal recovery system that can perform the write leveling operation by a recovered clock signal and a recovered DQS signal obtained by performing signal recovery operations upon the frequency-divided clock signals and the frequency-divided DQS signals, and an associated storage device are urgently needed. SUMMARY OF THE INVENTION It is therefore one of the objectives of the present invention to provide a signal recovery system that can perform a write leveling operation by frequency division and signal recovery, and an associated storage device, to address the above-mentioned issues. According to an embodiment of the present invention, a signal recovery system is provided. The signal recovery system may comprise multiple frequency dividers, multiple signal recovery circuits, and a data signal generating circuit. The multiple frequency dividers may be arranged to perform a frequency dividing operation upon a clock signal and a data strobe signal, respectively, to generate a set of frequency-divided clock signals and a set of frequency-divided data strobe signals. The multiple signal recovery circuits may be arranged to perform a signal recovery operation upon the set of frequency-divided clock signals and the set of frequency-divided data strobe signals, respectively, to generate a recovered clock signal and a recovered data strobe signal. The data signal generating circuit may be arranged to generate a data signal according to the recovered clock signal and the recovered data strobe signal, for indicating whether a rising edge of the data strobe signal is located at a first level or a second level of the clock signal, wherein the first level is higher than the second level. According to an embodiment of the present invention, a storage device is provided. The storage device may comprise a memory controller, a memory, multiple signal recovery circuits, and a data signal generating circuit. The memory may comprise multiple frequency dividers, wherein the multiple frequency dividers may be arranged to receive a clock signal and a data strobe signal from the memory controller, and perform a frequency dividing operation upon the clock signal and the data strobe signal, respectively, to generate a set of frequency-divided clock signals and a set of frequency-divided data strobe signals. The multiple signal recovery circuits may be arranged to perform a signal recovery operation upon the set: of frequency-divided clock signals and the set of frequency-divided data strobe signals, respectively, to generate a recovered clock signal and a recovered data strobe signal. The data signal generating circuit may be arranged to generate a data signal according to the recovered clock signal and the recovered data strobe signal, and transmit the data signal to the memory controller, for indicating whether a rising edge of the data strobe signal is located at a first level or a second level of the clock signal, wherein the first level is higher than the second level. One