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US-12627306-B2 - Oscillator calibrated to a microelectromechanical system (MEMS) resonator-based oscillator

US12627306B2US 12627306 B2US12627306 B2US 12627306B2US-12627306-B2

Abstract

In one example, an apparatus comprises an oscillator having a control input and a clock output. The apparatus also comprises a frequency control circuit having an input and a control output, the control output coupled to the control input, and a reference clock generator having a reference clock output. The apparatus also comprises a multiplexer having a first multiplexer input, a second multiplexer input, a selection input, and a multiplexer output, the first multiplexer input coupled to the clock output, the second multiplexer input coupled to the reference clock output, and the multiplexer output coupled to the input of the frequency control circuit.

Inventors

  • Bichoy BAHR
  • Yogesh Ramadass

Assignees

  • TEXAS INSTRUMENTS INCORPORATED

Dates

Publication Date
20260512
Application Date
20240830

Claims (20)

  1. 1 . An apparatus comprising: an oscillator having a control input and a clock output; a frequency control circuit having an input and a control output, the control output coupled to the control input; a reference clock generator having a reference clock output; and a multiplexer having a first multiplexer input, a second multiplexer input, a selection input, and a multiplexer output, the first multiplexer input coupled to the clock output, the second multiplexer input coupled to the reference clock output, and the multiplexer output coupled to the input of the frequency control circuit.
  2. 2 . The apparatus of claim 1 , wherein the oscillator and the reference clock generator have different frequency variations with respect to a physical condition.
  3. 3 . The apparatus of claim 2 , wherein the physical condition includes at least one of: a respective temperature of each of the oscillator and the reference clock generator, a respective stress received by each of the oscillator and the reference clock generator, or a respective age of each of the oscillator and the reference clock generator.
  4. 4 . The apparatus of claim 1 , wherein the oscillator includes a voltage-controlled oscillator (VCO).
  5. 5 . The apparatus of claim 4 , wherein the VCO includes a ring oscillator.
  6. 6 . The apparatus of claim 1 , wherein the reference clock generator includes a microelectromechanical system (MEMS) resonator.
  7. 7 . The apparatus of claim 6 , wherein the MEMS resonator includes a bulk acoustic wave (BAW) resonator.
  8. 8 . The apparatus of claim 1 , wherein the oscillator and the reference clock generator have different temperature coefficients.
  9. 9 . The apparatus of claim 1 , wherein the frequency control circuit includes a first circuit configured to: convert a clock signal at the input to a first voltage; and provide a frequency control signal at the control output based on the first voltage and a reference voltage.
  10. 10 . The apparatus of claim 9 , further comprising control logic coupled to the multiplexer and configured to: in a first mode, control the multiplexer to connect the reference clock output to the input of the frequency control circuit to set the reference voltage based on the first voltage; and in a second mode, control the multiplexer to connect the clock output to the input of the frequency control circuit to set the frequency control signal based on a difference between the first voltage and the reference voltage.
  11. 11 . The apparatus of claim 10 , wherein the frequency control circuit includes: a phase generator having an input coupled to the input of the frequency control circuit; a resistor coupled to a ground terminal; a switched-capacitor resistor (SCR) coupled between a power supply and the resistor, the SCR having inputs coupled to outputs of the phase generator, the phase generator, the switched-capacitor resistor, and the resistor configured to provide the first voltage; a digital-to-analog converter (DAC) coupled to the control logic and configured to provide the reference voltage; and an integrator coupled to an output of the DAC and the SCR, the integrator having an output coupled to the output of the frequency control circuit and configured to provide the frequency control signal based on integrating the difference between the first voltage and the reference voltage.
  12. 12 . The apparatus of claim 11 , further comprising a temperature sensor coupled to at least one of the control logic or the DAC, wherein the at least one of the control logic or the DAC is configured to adjust the reference voltage based on a signal from the temperature sensor.
  13. 13 . The apparatus of claim 11 , further comprising an analog-to-digital converter (ADC) having an input coupled to the SCR and an output coupled to the control logic, the ADC configured to convert the first voltage to digital values, and provide the digital values to the control logic; and wherein the control logic is configured to, in the second mode, provide the digital values to the DAC to generate the reference voltage.
  14. 14 . The apparatus of claim 13 , wherein the ADC and the DAC are part of a sigma-delta modulator.
  15. 15 . The apparatus of claim 11 , wherein the SCR is a first SCR, the resistor is a first resistor, and the frequency control circuit includes a second resistor coupled to the ground terminal and a second SCR coupled between the power supply and the second resistor, the second SCR has inputs coupled to the outputs of the phase generator; and wherein the control logic is configured to: in the first mode, connect the first SCR, the second SCR, the first resistor, and the second resistor to the integrator to provide the first voltage; and in the second mode, disconnect the second SCR and the second resistor from the integrator.
  16. 16 . The apparatus of claim 1 , further comprising a frequency divider coupled between the reference clock output and the second multiplexer input.
  17. 17 . The apparatus of claim 1 , wherein the oscillator, the frequency control circuit, the reference clock generator, and the multiplexer are part of an integrated circuit, the integrated circuit further comprising a second circuit having a clock input coupled to the clock output.
  18. 18 . An integrated circuit (IC), comprising: a clock circuit having a first output, the clock circuit including: an oscillator having a control input and a clock output; a frequency control circuit having an input and a control output, the control output coupled to the control input; a reference clock generator having a reference clock output; and a multiplexer having a first multiplexer input, a second multiplexer input, a selection input, and a multiplexer output, the first multiplexer input coupled to the clock output, the second multiplexer input coupled to the reference clock output, and the multiplexer output coupled to the input of the frequency control circuit; and a second circuit having a clock input coupled to the clock output.
  19. 19 . The IC of claim 18 , wherein the oscillator and the reference clock generator have different frequency variations with respect to a physical condition.
  20. 20 . The IC of claim 19 , wherein the physical condition includes at least one of: a respective temperature of each of the oscillator and the reference clock generator, a respective stress received by each of the oscillator and the reference clock generator, or a respective age of each of the oscillator and the reference clock generator.

Description

CROSS-REFERENCE TO RELATED APPLICATION This nonprovisional application is a continuation of U.S. patent application Ser. No. 17/936,505, filed Sep. 29, 2022, which is hereby incorporated by reference in its entirety. BACKGROUND Oscillators generate clock signals used in a variety of applications with varying degrees of accuracy and stability requirements. One type of oscillator is a crystal oscillator. However, crystal oscillators are bulky, costly, and difficult to integrate on a semiconductor device containing the circuitry using the clock signal. A resistor-capacitor (R-C) oscillator can be integrated on the same die as the circuit using its clock signal but suffers from stability problems, high Allan deviation (representing fractional frequency fluctuation), high temperature coefficient of frequency (TCF), and random telegraph noise (RTN). SUMMARY In one example, a clock circuit includes a voltage-controlled oscillator (VCO) having a control input and a first clock output. The clock circuit includes a frequency-locked loop (FLL) having an FLL input and a control output, the control output coupled to the control input. A microelectromechanical system (MEMS) resonator-based oscillator has a second clock output. A multiplexer has a first multiplexer input, a second multiplexer input, a selection input, and a multiplexer output. The first multiplexer input is coupled to the first clock output. The second multiplexer input is coupled to the second clock output. The multiplexer output is coupled to the FLL input. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a clock circuit in an example. FIG. 2 is a schematic of a clock circuit that includes a switched-capacitor resistor and a voltage-controlled ring oscillator in an example. FIG. 3 is a schematic of a clock circuit that a frequency-locked loop (FLL), a voltage-controlled ring oscillator, and a microelectromechanical system (MEMS) resonator-based oscillator to calibrate the FLL in an example. FIG. 4 is cut-away view of a bulk acoustic wave (BAW) resonator in an example. FIG. 5 is a schematic of a clock circuit that a frequency-locked loop (FLL), a voltage-controlled ring oscillator, and a microelectromechanical system (MEMS) resonator-based oscillator to calibrate the FLL in another example. FIG. 6 is an example of multiple switched-capacitor resistors and reference resistors usable in the example clock circuit of FIG. 5. DETAILED DESCRIPTION The same reference numbers or other reference designators are used in the drawings to designate the same or similar (either by function and/or structure) features. The embodiments described herein are directed to a clock circuit that includes an oscillator and a microelectromechanical system (MEMS) resonator-based oscillator. The MEMS resonator-based oscillator is used to calibrate the clock circuit. FIG. 1 is a block diagram of a clock circuit 100 in accordance with an example. The clock circuit 100 in FIG. 1 includes a voltage-controlled oscillator (VCO) 110, a frequency-locked loop (FLL) 120, a MEMS resonator-based 130, a frequency divider 140, a selection circuit 150, and control logic 160. The output signal from the VCO 110 is the output clock signal, CKOUT. In one example, the selection circuit 150 is an analog voltage multiplexer having a 0-input and a 1-input. The output clock signal CKOUT is coupled to the 0-input of the selection circuit 150. The MEMS resonator-based oscillator 130 generates a clock signal labeled F1. The frequency of F1 may be substantially higher than the frequency of CKOUT. For example, the frequency of F1 may be 2.5 GHZ, while the frequency of CKOUT may be 32 KHz. The frequency divider 140 receives F1 as an input signal and divides down the frequency of F1 to produce and output clock labeled F1div. The divide ratio implemented by the frequency divider 140 may be such that the frequency of F1div is approximately equal to the frequency of CKOUT. Clock signal F1div is provided to the 1-input of the selection circuit 150. The control logic 160 generates a selection signal (SEL1) to a control input of the selection circuit. In one logic state (e.g., logic low), the selection signal SEL1 causes the selection circuit to provide the CKOUT clock signal on its 0-input to the selection circuit's output. In the other logic state (e.g., logic high), the selection signal SEL1 causes the selection circuit to provide the F1div clock signal on its 1-input to the selection circuit's output. When not performing a calibration process (e.g., after completion of the calibration process), the control logic 160 controls the selection circuit 150 so as to provide CKOUT into the input of the FLL 120. The FLL 120 generates an internal reference voltage, VREF (shown in FIGS. 2-4). The FLL 120 also generates a second voltage whose amplitude is related to the frequency of CKOUT. The FLL 120 includes an integrator that integrates the difference between VREF and the second voltage. Both voltages are gene