US-12627308-B2 - Stimulation and recording system with multi-point artifact cancellation

Abstract

A system and method for reducing or eliminating undesired effects of an artifact on a received signal is disclosed. The signal is generated from stimulating a sample. A receiver includes estimations of artifacts on the signal that are subtracted at different stages of the receiver. The estimations of the artifact may be performed via a successive approximation register scheme.

Inventors

• Hossein Hashemi
• Aria SAMIEI

Assignees

• UNIVERSITY OF SOUTHERN CALIFORNIA

Dates

Publication Date

20260512

Application Date

20221114

Claims (20)

1. 1 . A signal recorder and stimulator system comprising: a stimulation electrode operable to be attached to a sample; a signal generator coupled to the stimulation electrode to provide a stimulation signal to the sample; a detection electrode operable to be attached to the sample; a signal recorder including: an input coupled to the detection electrode, the input receiving an input signal from the sample stimulated by the stimulation signal applied by the stimulation electrode, the input signal including an artifact; a first artifact estimation logic circuit coupled to the input producing a first artifact estimate; a first subtraction logic circuit subtracting the first artifact estimation from the input signal to produce a first artifact cancelled signal; a first low noise amplifier (LNA) receiving the first artifact cancelled signal and outputting an amplified first artifact cancelled signal; a second artifact estimation logic circuit coupled to the input signal producing a second residual artifact estimate; a second subtraction logic circuit coupled to the first subtraction logic circuit, the second subtraction logic circuit subtracting the estimate of the second residual artifact from the amplified first artifact cancelled signal to produce a second artifact cancelled signal; and an analog to digital converter (ADC) receiving the second artifact cancelled signal and outputting an output signal.
2. 2 . The signal recorder and stimulator system of claim 1 , wherein the first and second estimation logic include a successive approximation register (SAR) scheme to estimate the estimation artifacts from the input signal.
3. 3 . The signal recorder and stimulator system of claim 1 , wherein the first artifact estimation logic includes a common mode estimation logic for estimation of common mode of the artifact, and a differential mode estimation logic for estimation of differential mode of the artifact.
4. 4 . The signal recorder and stimulator system of claim 1 , wherein the stimulation signal stimulates a selected neuron or neurons of the sample.
5. 5 . The signal recorder and stimulator system of claim 1 , wherein the signal recorder is a system-on-chip (SoC).
6. 6 . The signal recorder and stimulator system of claim 1 , further comprising: an electrode coupled to the input; a second low-noise amplifier (LNA) configured to receive the input signal from the electrode; a gain amplifier configured to adjust a level of the electrical signals to a level appropriate for the ADC; a filter configured to remove noise from the input signal; and a digital signal processor (DSP) coupled to the ADC.
7. 7 . The signal recorder and stimulator system of claim 6 , wherein the DSP is further configured to estimate and subtract a third residual stimulation artifact from the output signal from the ADC.
8. 8 . The signal recorder and stimulator system of claim 7 , wherein the first estimation of the artifact is subtracted from the input signal by the first subtraction logic at a first point before the LNA to cancel the artifact at a first point; and wherein the second estimate of the residual artifact is subtracted from the input signal by the second subtraction logic at a second point before the gain amplifier.
9. 9 . The signal recorder and stimulator system of claim 8 , further comprising: a first digital-to-analog converter (DAC) configured to convert a digital representation of the first artifact estimation into an analog waveform; and a second DAC configured to convert a digital representation of the second artifact estimation into an analog waveform.
10. 10 . The signal recorder and stimulator system of claim 6 , further comprising: a plurality of electrodes for receiving stimulation signals including the electrode; a plurality of inputs including the input, each of the inputs coupled to one of the plurality of inputs; multiple front end circuits, each having a stimulator and a low noise amplifier and defining a signal channel, wherein the low noise amplifier is part of one the multiple front end circuits, wherein each of the front end circuits are coupled to one of a plurality of inputs; and a multiplexer sending signals selected from the plurality of front end circuit to a back end circuit including the gain amplifier.
11. 11 . The signal recorder and stimulator system of claim 10 further comprising an offset circuit coupled to each of the channels.
12. 12 . The signal recorder and stimulator system of claim 1 , wherein the artifact is one or more of electrical stimulation, magnetic stimulation, optical stimulation, or acoustic stimulation.
13. 13 . The signal recorder and stimulator system of claim 1 , wherein a least-mean-square (LMS) algorithm trains the coefficients a finite-impulse-response (FIR) or infinite-impulse-response (IIR) filter to estimate the artifact.
14. 14 . The signal recorder and stimulator system of claim 1 , further comprising a memory storing the first artifact estimation and the second artifact estimation, wherein the signal recorder includes an estimation phase to collect data from the input signal for determining the first and second artifact estimations.
15. 15 . A method of canceling an artifact on an input signal generated from a sample by a stimulation signal, the method comprising: attaching a stimulation electrode to the sample; providing the stimulation signal to the sample via a signal generator coupled to the stimulation electrode; attaching a detection electrode to the sample; receiving the input signal from the detection electrode from the sample; determining a first estimation of the artifact via a first estimation logic circuit; determining a second artifact estimation of a residual of the artifact on the input signal via a second estimation logic circuit; subtracting the first artifact estimation from the input signal to produce a first artifact canceled signal that is input to a low noise amplifier; and subtracting the second artifact estimation from an output signal from the low noise amplifier to produce a second artifact canceled signal; sending the second artifact canceled signal to a gain amplifier.
16. 16 . The method of claim 15 , wherein the determination of the first and second artifact estimation is performed by a successive approximation register (SAR) scheme.
17. 17 . The method of claim 15 , wherein the determination of the first artifact estimation includes estimating a common mode of the artifact, and estimating a differential mode of the artifact.
18. 18 . The method of claim 15 , further comprising estimating and subtracting a third residual stimulation artifact from the input signal via a digital signal processor.
19. 19 . The method of claim 15 , wherein the artifact is one or more of electrical stimulation, magnetic stimulation, optical stimulation, or acoustic stimulation.
20. 20 . The method of claim 15 , further comprising: storing the first artifact estimation and the second artifact estimation in a memory, wherein the determination of the first artifact estimation and second artifact estimation is determined in an estimation phase to collect data from the input signal; and wherein the subtraction of the first and second artifact estimations is performed in a cancelation phase; and repeating the estimation phase in response to a changed condition.

Description

PRIORITY CLAIM This disclosure claims priority to and the benefit of U.S. Provisional Ser. No. 63/279,279 filed on Nov. 15, 2021. The contents of that application are hereby incorporated in their entirety. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT This invention was made with government support under Grant Nos. NS099703 awarded by National Institutes of Health and CBET1343193 awarded by the National Science Foundation. The government has certain rights in the invention. FIELD The present disclosure relates to systems that include signal generation and signal recording functions. Specifically, certain aspects of the disclosure relate to biomedical systems that include electrical, magnetic, optical and acoustic stimulation and recording functions. BACKGROUND Currently, responsive neurostimulation (RNS) systems are being surgically implanted in patients with epilepsy. These devices continuously monitor the electrocorticography (ECoG) signals and look for patterns that can lead to seizures. Once the pattern is detected, stimulation signals are delivered to depth electrodes to prevent seizures. However, such devices lack the capability of simultaneous stimulation and recording of neural signals. Closed-loop brain-machine interfaces have become critical components in neuroscience research and clinical applications such as the RNS systems for epilepsy. These systems record the neural activity, perform signal processing algorithms, and generate a specific spatiotemporal pattern to stimulate the neurons in the brain. Unfortunately, stimulation of the brain tissue introduces an artifact at the recording channels, which can significantly degrade the received signal quality. One approach to overcome the artifact issue is to use oversampling analog to digital converters (ADCs) to increase the linear dynamic range (DR) of the front-end (FE) and accommodate the large artifacts on top of the neural signals. However, increasing the ADC resolution from a conventional 10 bits to ˜15 bits (equivalent to 30 dB boost in dynamic range) drastically increases the energy required for the raw data transmission or on-chip back-end digital processing for artifact removal. An alternative approach is to estimate and cancel the artifact at the front end using adaptive digital filters, which can potentially relax the dynamic response requirements of the ADC. However, the existing front end cancellation techniques provide a limited artifact suppression (<40 dB) which reduces a 1000 mVpp artifact to about 10 mVpp swing. This residual artifact is about 1-2 orders of magnitude larger than the action potentials and the local field potentials (50-500 μVpp), which limits the effective number of bits (ENOB) allocated to the quantization of the target neural signals. In many systems, it is advantageous or necessary to allow for simultaneous stimulation and recording of electrical signals. For instance, some biomedical systems should record physiological or neural signals while simultaneously providing appropriate stimulation signals to the tissues or neurons. In these systems, influences on the stimulation signal can directly or indirectly corrupt the recordings. Such influences are references such as signal artifacts that may be a result of external or internal sources. Existing methods that facilitate simultaneous recording and stimulation are bulky, consume significant power, require technologies that support high voltages, and often are unable to completely or meaningfully remove the undesired effects of stimulation signals from the recordings. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present disclosure as set forth in the remainder of the present application with reference to the drawings. SUMMARY One disclosed example is a signal recorder for a stimulation system that has an input receiving an input signal from a sample stimulated by a stimulation signal. The input signal includes an artifact. A first artifact estimation logic is coupled to the input producing a first artifact estimate. A first subtraction logic subtracts the first artifact estimation from the input signal. A second artifact estimation logic is coupled to the input signal producing a second residual artifact estimate. A second subtraction logic subtracts the estimate of the residual stimulation artifact from the input signal. An analog to digital converter (ADC) receives the input signal after subtraction of the estimates of the artifact and outputs an output signal. Another disclosed example is a method of canceling an artifact on an input signal generated from a sample by a stimulation signal. The input signal is measured from the sample. A first estimation of the artifact is determined. A second artifact estimation of a residual of the artifact on the input signal is determined. The first artifact estimation is subtracte