US-12627310-B2 - AVS architecture for SAR ADC

Abstract

An Integrated Circuit (IC) includes one or more functional circuits of a given type, a test circuit including a selected one of the functional circuits or a replica circuit of the same type as the functional circuits, and an Adaptive Voltage Scaling (AVS) circuit. The AVS circuit is configured to determine a delay of the test circuit, and to adjust a supply voltage of the functional circuits in response to the determined delay of the test circuit.

Inventors

• Benjamin Tomas Reyes
• Gabriele MINOIA
• Ray Luan Nguyen

Assignees

• MARVELL ASIA PTE LTD

Dates

Publication Date

20260512

Application Date

20240117

Claims (18)

1. 1 . An Integrated Circuit (IC), comprising: one or more functional circuits of a given type; a test circuit, comprising a selected one of the functional circuits or a replica circuit of a same type as the functional circuits, the test circuit configured to generate a signal indicative of a delay of the test circuit; and an Adaptive Voltage Scaling (AVS) circuit comprising: a Time-to-Digital Conversion circuit (TDC), configured to convert a reference clock into a first digital value, and to convert the signal indicative of a delay of the test circuit into a second digital value; and logic, configured to adjust a supply voltage of the functional circuits based on a difference between the first digital value and the second digital value produced by the TDC.
2. 2 . The IC according to claim 1 , wherein: the functional circuits comprise Analog-to-Digital Converters (ADCs) and the test circuit comprises a test ADC; and the delay of the test circuit comprises a conversion delay of the test ADC, the conversion delay being a time duration needed for converting an analog input value into a corresponding digital value.
3. 3 . The IC according to claim 2 , wherein each of the functional ADCs, and the test ADC, comprise Successive Approximation Register (SAR) ADCs, each ADC having a respective variable conversion delay.
4. 4 . The IC according to claim 2 , wherein the or more functional ADCs comprise a multiplicity of one functional ADCs configured to sample respective mutually-delayed replicas of an input signal at a first sampling rate, thereby forming an interleaved ADC that samples the input signal at a second sampling rate, higher than the first sampling rate.
5. 5 . The IC according to claim 2 , wherein the signal indicative of the delay comprises an End-of-Conversion (EoC) signal indicative of completion of each conversion operation.
6. 6 . The IC according to claim 1 , further comprising a power supply having an output that is adjustable, the power supply being configured to provide the supply voltage of the functional circuits, wherein the AVS circuit is configured to control the adjustable power supply to adjust the supply voltage of the functional circuits.
7. 7 . The IC according to claim 1 , wherein the AVS circuit is configured to determine the delay of the test circuit for multiple values of the supply voltage, and to set the supply voltage to a value that minimizes a power consumption of the functional circuits.
8. 8 . The IC according to claim 1 , wherein the AVS circuit is configured to determine the delay of the test circuit for multiple values of the supply voltage, and to set the supply voltage to a value that minimizes a power consumption of the functional circuits while still meeting a speed requirement of the functional circuit.
9. 9 . The IC according to claim 1 , wherein the AVS circuit is configured to determine the delay of the test circuit for multiple values of the supply voltage, and to set the supply voltage to a value that minimizes a power consumption the functional circuit but is greater than a preset minimal voltage.
10. 10 . An Adaptive Voltage Scaling (AVS) method, comprising: performing the following in an Integrated Circuit (IC) that includes (i) one or more functional circuits of a given type and (ii) a test circuit, comprising a selected one of the functional circuits or a replica circuit of a same type as the functional circuits, the test circuit configured to generate a signal indicative of a delay of the test circuit: converting a reference clock into a first digital value using a Time-to-Digital Conversion circuit (TDC); converting the signal indicative of the delay of the test circuit into a second digital value using the TDC; and adjusting a supply voltage of the functional circuits based on a difference between the first digital value and the second digital value produced by the TDC.
11. 11 . The AVS method according to claim 10 , wherein: the functional circuits comprise Analog-to-Digital Converters (ADCs) and the test circuit comprises a test ADC; and the delay of the test circuit comprises a conversion delay of the test ADC, the conversion delay being a time duration needed for converting an analog input value into a corresponding digital value.
12. 12 . The AVS method according to claim 11 , wherein each of the functional ADCs, and the test ADC, comprise Successive Approximation Register (SAR) ADCs, each ADC having a respective variable conversion delay.
13. 13 . The AVS method according to claim 11 , wherein the one or more functional ADCs comprise a multiplicity of functional ADCs configured to sample respective mutually-delayed replicas of an input signal at a first sampling rate, thereby forming an interleaved ADC that samples the input signal at a second sampling rate, higher than the first sampling rate.
14. 14 . The AVS method according to claim 11 , wherein the signal indicative of the delay comprises an End-of-Conversion (EoC) signal indicative of completion of each conversion operation.
15. 15 . The AVS method according to claim 10 , wherein adjusting the supply voltage comprises controlling an adjustable power supply to adjust the supply voltage of the functional circuits.
16. 16 . The AVS method according to claim 10 , wherein determining the delay comprises determining the delay of the test circuit for multiple values of the supply voltage, and wherein adjusting the supply voltage comprises setting the supply voltage to a value that minimizes a power consumption of the functional circuits.
17. 17 . The AVS method according to claim 10 , wherein determining the delay comprises determining the delay of the test circuit for multiple values of the supply voltage, and wherein adjusting the supply voltage comprises setting the supply voltage to a value that minimizes a power consumption of the functional circuits while still meeting a speed requirement of the functional circuit.
18. 18 . The AVS method according to claim 10 , wherein determining the delay comprises determining the delay of the test circuit for multiple values of the supply voltage, and wherein adjusting the supply voltage comprises setting the supply voltage to a value that minimizes a power consumption the functional circuit but is greater than a preset minimal voltage.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application 63/439,767, filed Jan. 18, 2023, whose disclosure is incorporated herein by reference. FIELD OF THE DISCLOSURE The present disclosure relates generally to high-speed analog to digital converters (ADCs), and particularly to dynamic power setting of high-speed ADCs. BACKGROUND Adaptive Voltage Scaling (AVS) can be used to save power in high-speed ADCs. Without AVS, the ADC is traditionally designed to meet a specified timing requirement (e.g., minimum conversion rate) at all process corners and at the full range of operating temperatures (worst-case conditions). As a result, when the conditions are better than worst case conditions (e.g., a typical or a fast process corner), the ADC will consume unnecessarily high power. Conventional AVS systems typically measure the speed of a ring-oscillator to obtain an estimate of the IC speed at the given process corner and the current temperature, and then throttle the power supply voltage (and, thus, change the power consumption). In some cases, the power consumption is set to a minimum level that still safely meets a given speed requirement; in other cases, the speed is set to a maximum level that still safely meets a given power consumption budget. SUMMARY An embodiment that is described herein provides an Integrated Circuit (IC) including one or more functional circuits of a given type, a test circuit including a selected one of the functional circuits or a replica circuit of the same type as the functional circuits, and an Adaptive Voltage Scaling (AVS) circuit. The AVS circuit is configured to determine a delay of the test circuit, and to adjust a supply voltage of the functional circuits in response to the determined delay of the test circuit. In some embodiments, the functional circuits include Analog-to-Digital Converters (ADCs) and the test circuit includes a test ADC, and the AVS circuit is configured to determine a conversion delay of the test ADC, the conversion delay being a time duration needed for converting an analog input value into a corresponding digital value. In an example embodiment, each of the functional ADCs, and the test ADC, include Successive Approximation Register (SAR) ADCs, each ADC having a respective variable conversion delay. In a disclosed embodiment, the one or more functional ADCs include a multiplicity of functional ADCs configured to sample respective mutually-delayed replicas of an input signal at a first sampling rate, thereby forming an interleaved ADC that samples the input signal at a second sampling rate, higher than the first sampling rate. In an embodiment, the test ADC is configured to output an End-of-Conversion (EoC) signal indicative of completion of each conversion operation, and the AVS circuit is configured to determine the conversion delay responsively to the EoC signal. In an example embodiment, the AVS circuit includes (i) a Time-to-Digital Conversion circuit (TDC), which is configured to convert a reference clock to a first digital value, and to convert the EoC signal to a second digital value, and (ii) logic, configured to generate a voltage correction instruction based on a difference between the first digital value and the second digital value. In some embodiments, the IC further includes a power supply having an output that is adjustable, the power supply being configured to provide the supply voltage of the functional circuits, and the AVS circuit is configured to control the adjustable power supply to adjust the supply voltage of the functional circuits. In an embodiment, the AVS circuit is configured to determine the delay of the test circuit for multiple values of the supply voltage, and to set the supply voltage to a value that minimizes a power consumption of the functional circuits. In an embodiment, the AVS circuit is configured to determine the delay of the test circuit for multiple values of the supply voltage, and to set the supply voltage to a value that minimizes a power consumption of the functional circuits while still meeting a speed requirement of the functional circuit. In an embodiment, the AVS circuit is configured to determine the delay of the test circuit for multiple values of the supply voltage, and to set the supply voltage to a value that minimizes a power consumption the functional circuit but is greater than a preset minimal voltage. There is additionally provided, in accordance with an embodiment described herein, an Adaptive Voltage Scaling (AVS) method in an Integrated Circuit (IC) that includes (i) one or more functional circuits of a given type and (ii) a test circuit including a selected one of the functional circuits or a replica circuit of a same type as the functional circuits. The method includes determining a delay of the test circuit, and adjusting a supply voltage of the functional circuits in response to the determined delay of the test circuit. The pres