US-12627313-B2 - Successive approximation register analog to digital converter and signal conversion method

Abstract

A successive approximation register analog to digital converter includes a capacitor array circuit, a quantizer circuit, a delay adjustment circuit, a control logic circuit, and a detector circuitry. The capacitor array circuit samples input signals to generate first signals and is sequentially switched according to a first digital code. The quantizer circuit quantizes the first signals according to a first control signal to generate second signals and receives the first control signal via a signal path. The delay adjustment circuit is coupled in parallel with the signal path and selectively adjusts a propagation delay of the first control signal. The control logic circuit generates the first digital code according to the second signals. The detector circuitry detects whether a quantization of the quantizer circuit is completed to generate the first control signal.

Inventors

• Shih-Hsiung Huang

Assignees

• REALTEK SEMICONDUCTOR CORPORATION

Dates

Publication Date

20260512

Application Date

20231212

Priority Date

20221216

Claims (18)

1. 1 . A successive approximation register analog to digital converter, comprising: a capacitor array circuit configured to sample a plurality of input signals to generate a plurality of first signals, wherein the capacitor array circuit is sequentially switched according to a first digital code; a quantizer circuit configured to quantize the plurality of first signals according to a first control signal to generate a plurality of second signals, wherein the quantizer circuit receives the first control signal via a signal path; a delay adjustment circuit coupled in parallel with the signal path and configured to selectively adjust a propagation delay of the first control signal; a control logic circuit configured to generate the first digital code according to the plurality of second signals; a detector circuitry configured to detect whether a quantization of the quantizer circuit is completed to generate the first control signal; and a delay control circuit configured to generate a second control signal according to the plurality of second signals and a plurality of bits, wherein the detector circuitry is configured to perform a counting operation according to the plurality of second signals to sequentially generate the plurality of bits, and the delay adjustment circuit is further configured to set the propagation delay according to the second control signal.
2. 2 . The successive approximation register analog to digital converter of claim 1 , wherein the delay adjustment circuit comprises: a plurality of delay cell circuits configured to adjust a capacitance value of the signal path according to a second control signal, in order to set the propagation delay.
3. 3 . The successive approximation register analog to digital converter of claim 2 , wherein one of the plurality of delay cell circuits comprises: a first transistor, wherein a first terminal of the first transistor receives a corresponding bit of the second control signal, and the first terminal of the first transistor is coupled to a second terminal of the first transistor; an inverter circuit, wherein an input terminal of the inverter circuit is coupled to the second terminal of the first transistor; and a second transistor, wherein a first terminal and a second terminal of the second transistor are coupled to an output terminal of the inverter circuit, and a control terminal of the first transistor and a control terminal of the second transistor are coupled to the signal path.
4. 4 . The successive approximation register analog to digital converter of claim 3 , wherein a conductivity type of the first transistor is opposite to a conductivity type of the second transistor.
5. 5 . The successive approximation register analog to digital converter of claim 4 , wherein the first transistor is a P-type transistor, and the second transistor is an N-type transistor.
6. 6 . The successive approximation register analog to digital converter of claim 2 , wherein one of the plurality of delay cell circuits comprises: a switch configured to be selectively turned on according to a corresponding bit of the second control signal; and a capacitive element coupled to the signal path via the switch.
7. 7 . The successive approximation register analog to digital converter of claim 1 , wherein the quantizer circuit is further configured to selectively reset the plurality of second signals according to the first control signal.
8. 8 . The successive approximation register analog to digital converter of claim 1 , wherein the detector circuitry is configured to perform a counting operation according to the plurality of second signals to sequentially generate a plurality of bits, and generate the first control signal according to a last bit in the plurality of bits.
9. 9 . The successive approximation register analog to digital converter of claim 1 , wherein the detector circuitry comprises: a first logic gate circuit configured to generate a valid signal according to the plurality of second signals; a counter circuit configured to sequentially generate a plurality of bits according to the valid signal and a clock signal; and a second logic gate circuit configured to generate the first control signal according to the valid signal, the clock signal, and a last bit in the plurality of bits.
10. 10 . A successive approximation register analog to digital converter, comprising: a capacitor array circuit configured to sample a plurality of input signals to generate a plurality of first signals, wherein the capacitor array circuit is sequentially switched according to a first digital code; a quantizer circuit configured to quantize the plurality of first signals according to a first control signal to generate a plurality of second signals, wherein the quantizer circuit receives the first control signal via a signal path; a delay adjustment circuit coupled in parallel with the signal path and configured to selectively adjust a propagation delay of the first control signal; a control logic circuit configured to generate the first digital code according to the plurality of second signals; and a detector circuitry configured to detect whether a quantization of the quantizer circuit is completed to generate the first control signal, wherein the propagation delay is configured to adjust a start time of the quantization.
11. 11 . A signal conversion method, comprising: sampling, by a capacitor array circuit, a plurality of input signals to generate a plurality of first signals, wherein the capacitor array circuit is sequentially switched according to a first digital code; quantizing, by a quantizer circuit, the plurality of first signals according to a first control signal to generate a plurality of second signals, wherein the quantizer circuit receives the first control signal via a signal path; selectively adjusting, by a delay adjustment circuit, a propagation delay of the first control signal, wherein the delay adjustment circuit and the signal path are coupled in parallel with each other; generating the first digital code according to the plurality of second signals; detecting whether a quantization of the quantizer circuit is completed to generate the first control signal; and generating a second control signal according to the plurality of second signals and a plurality of bits, wherein the plurality of bits are generated by performing a counting operation according to the plurality of second signals, and the delay adjustment circuit is further configured to set the propagation delay according to the second control signal.
12. 12 . The signal conversion method of claim 11 , wherein the propagation delay is configured to adjust a start time of the quantization.
13. 13 . The signal conversion method of claim 11 , wherein the delay adjustment circuit comprises a plurality of delay cell circuits, and the plurality of delay cell circuits are configured to adjust a capacitance value of the signal path according to a second control signal, in order to set the propagation delay.
14. 14 . The signal conversion method of claim 13 , wherein one of the plurality of delay cell circuits comprises: a first transistor, wherein a first terminal of the first transistor receives a corresponding bit of the second control signal, and the first terminal of the first transistor is coupled to a second terminal of the first transistor; an inverter circuit, wherein an input terminal of the inverter circuit is coupled to the second terminal of the first transistor; and a second transistor, wherein a first terminal and a second terminal of the second transistor are coupled to an output terminal of the inverter circuit, and a control terminal of the first transistor and a control terminal of the second transistor are coupled to the signal path.
15. 15 . The signal conversion method of claim 14 , wherein a conductivity type of the first transistor is opposite to a conductivity type of the second transistor.
16. 16 . The signal conversion method of claim 13 , wherein one of the plurality of delay cell circuits comprises: a switch configured to be selectively turned on according to a corresponding bit of the second control signal; and a capacitive element coupled to the signal path via the switch.
17. 17 . The signal conversion method of claim 11 , wherein the quantizer circuit is further configured to selectively reset the plurality of second signals according to the first control signal.
18. 18 . The signal conversion method of claim 11 , wherein detecting whether the quantization of the quantizer circuit is completed to generate the first control signal comprises: performing a counting operation according to the plurality of second signals to sequentially generate a plurality of bits; and generating the first control signal according to a last bit in the plurality of bits.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present disclosure relates to a successive approximation register analog to digital converter, especially to a successive approximation register analog to digital converter with a delay adjustment mechanism and a signal conversion method thereof. 2. Description of Related Art In an analog-to-digital converter that employs capacitor array circuit(s) for signal conversion, the analog-to-digital converter usually performs a quantization in a fixed period, and the capacitor array circuit usually takes some time to be stabilized during the switching process. However, due to practical non-ideal factors, the stabilization time required for each capacitor in the capacitor array circuit after switching may be different, such that not all capacitors can be completely stable in the same fixed time. Thus, if the analog to digital converter starts the next quantization while the capacitor array circuit is not fully stabilized, the digital signal generated by the analog to digital converter will be different from the digital signal that is generated after the capacitor array circuit is fully stabilized, resulting in reduced output resolution. SUMMARY OF THE INVENTION In some aspects, an object of the present disclosure is to, but not limited to, provide a successive approximation register analog to digital converter with a delay adjustment mechanism and a signal conversion method thereof, in order to make an improvement to the prior art. In some aspects, a successive approximation register analog to digital converter includes a capacitor array circuit, a quantizer circuit, a delay adjustment circuit, a control logic circuit, and a detector circuitry. The capacitor array circuit is configured to sample a plurality of input signals to generate a plurality of first signals, in which the capacitor array circuit is sequentially switched according to a first digital code. The quantizer circuit is configured to quantize the plurality of first signals according to a first control signal to generate a plurality of second signals, in which the quantizer circuit receives the first control signal via a signal path. The delay adjustment circuit is coupled in parallel with the signal path and is configured to selectively adjust a propagation delay of the first control signal. The control logic circuit is configured to generate the first digital code according to the plurality of second signals. The detector circuitry is configured to detect whether a quantization of the quantizer circuit is completed to generate the first control signal. In some aspects, a signal conversion method includes the following operations: sampling, by a capacitor array circuit, a plurality of input signals to generate a plurality of first signals, wherein the capacitor array circuit is sequentially switched according to a first digital code; quantizing, by a quantizer circuit, the plurality of first signals according to a first control signal to generate a plurality of second signals, wherein the quantizer circuit receives the first control signal via a signal path; selectively adjusting, by a delay adjustment circuit, a propagation delay of the first control signal, in which the delay adjustment circuit and the signal path are coupled in parallel with each other; generating the first digital code according to the plurality of second signals; and detecting whether a quantization of the quantizer circuit is completed to generate the first control signal. These and other objectives of the present disclosure will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments that are illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a schematic diagram of a successive approximation register analog-to-digital converter according to some embodiments of the present disclosure. FIG. 2A illustrates a schematic diagram of the delay adjustment circuit in FIG. 1 according to some embodiments of the present disclosure. FIG. 2B illustrates a schematic diagram of the delay cell circuit in FIG. 2A according to some embodiments of the present disclosure. FIG. 2C illustrates a schematic diagram of the delay cell circuit in FIG. 2A according to some embodiments of the present disclosure. FIG. 3A illustrates a schematic diagram of the detector circuitry in FIG. 1 according to some embodiments of the present disclosure. FIG. 3B illustrates a schematic diagram of the counter circuit in FIG. 3A according to some embodiments of the present disclosure. FIG. 4 illustrates a flow chart of operations performed by the delay control circuit in FIG. 1 according to some embodiments of the present disclosure. FIG. 5 illustrates a flow chart of a signal conversion method according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The terms used in this specific