US-12627314-B2 - Sigma-delta modulator with residue converter for low-offset measurement system

Abstract

A signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity. The sensor readout channel may include a sigma-delta modulator having a modulator input and a modulator output, first system-level chopping switches located at the modulator input, an auxiliary path comprising an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the sigma-delta modulator, second system-level chopping switches located downstream of the sigma-delta modulator and the auxiliary path, and a signal combiner configured to combine a modulator output signal generated by the sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal.

Inventors

• John L. Melanson
• Axel Thomsen
• Mucahit Kozak
• Paul Wilson
• Eric J. King

Assignees

• CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.

Dates

Publication Date

20260512

Application Date

20240417

Claims (20)

1. 1 . A signal processing system comprising: a sensor readout channel configured to convert an electronic signal into a digital quantity, the sensor readout channel comprising: a sigma-delta modulator having a modulator input and a modulator output; first system-level chopping switches located at the modulator input; an auxiliary path comprising an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the sigma-delta modulator; second system-level chopping switches located downstream of the sigma-delta modulator and the auxiliary path; and a signal combiner configured to combine a modulator output signal generated by the sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal.
2. 2 . The signal processing system of claim 1 , wherein the memory element comprises an integrator.
3. 3 . The signal processing system of claim 1 , further comprising an impedance for converting a sensed physical quantity into the electronic signal.
4. 4 . The signal processing system of claim 3 , wherein: the electronic signal is a voltage; and the impedance is a resistor configured to convert an electrical current into the voltage.
5. 5 . The signal processing system of claim 4 , wherein the sensor readout channel further comprises a digital accumulator configured to digitally integrate the combined output signal to generate the digital quantity representing a net amount of charge that has flowed through the impedance.
6. 6 . The signal processing system of claim 4 , wherein the digital quantity represents a net amount of charge that has been delivered from a battery coupled to the impedance.
7. 7 . The signal processing system of claim 1 , wherein the sensor readout channel further comprises a digital accumulator configured to digitally integrate the combined output signal to generate an accumulated combined output signal.
8. 8 . The signal processing system of claim 1 , wherein the sensor readout channel further comprises a digital accumulator configured to digitally integrate the modulator output signal to generate an accumulated modulator output signal, and the combiner is configured to combine the accumulated modulator output signal with the auxiliary path output signal to generate the combined output signal.
9. 9 . The signal processing system of claim 1 , further comprising an anti-aliasing filter coupled between an input for receiving the electronic signal and the modulator input.
10. 10 . The signal processing system of claim 1 , further comprising an adaptive gain element applied to the auxiliary path output in order to minimize signal-to-noise degradation due to non-idealities of analog components of the signal processing system.
11. 11 . The signal processing system of claim 1 , wherein the sigma-delta modulator comprises a 3-level quantizer.
12. 12 . The signal processing system of claim 11 , wherein the 3-level quantizer is configured to, during production test of the signal processing system, detect the combined output signal in response to a pilot signal injected into an input of the signal processing system to determine a threshold mismatch of the 3-level quantizer.
13. 13 . The signal processing system of claim 1 , wherein the auxiliary signal path is configured such that it is only enabled upon a readout request for the combined output signal.
14. 14 . The signal processing system of claim 1 , wherein the second system-level chopping switches are located at the output of the signal combiner.
15. 15 . The signal processing system of claim 1 , wherein the second system-level chopping switches are located at the input of the signal combiner.
16. 16 . The signal processing system of claim 1 , wherein the second system-level chopping switches are located at the input of the signal combiner and the output of the sigma-delta modulator.
17. 17 . The signal processing system of claim 1 , wherein the frequency of operation of the auxiliary path is at minimum twice a system chopping frequency for the first system-level chopping switches and the second system-level chopping switches.
18. 18 . The signal processing system of claim 17 , wherein the output path of the sigma-delta modulator includes a delay element and a downsampler.
19. 19 . The signal processing system of claim 18 , wherein the downsampler may downsample from a sampling frequency of the sigma-delta modulator to twice the system chopping frequency.
20. 20 . The signal processing system of claim 18 , wherein the delay element is designed to match a delay from an input of the auxiliary path to an output of the auxiliary path.

Description

RELATED APPLICATIONS This application is related to United States Patent Application Publication No. 2022/0263520, published Aug. 18, 2022, and U.S. Pat. No. 11,777,516, granted Oct. 3, 2023, both of which are incorporated by reference herein in their entireties. FIELD OF DISCLOSURE The present disclosure relates in general to circuits for electronic devices, including without limitation personal portable devices such as wireless telephones and media players, and more specifically, to a system having a sigma-delta modulator and an auxiliary path parallel to the sigma-delta modulator in order to minimize measurement offset. BACKGROUND Portable electronic devices, including wireless telephones, such as mobile/cellular telephones, tablets, cordless telephones, mp3 players, and other consumer devices, are in widespread use. Such portable electronic devices are often powered by a battery (e.g., a lithium-ion battery). In battery-powered devices, it is often desirable to measure an amount of electrical charge drawn from a battery and delivered to the battery, which may be used to determine a state of charge of the battery. A circuit referred to as a coulomb counter may be used to measure an amount of electrical charge drawn from a battery and delivered to the battery. In operation, a coulomb counter may detect an electrical current flowing in and out of the battery and integrate such current continuously over time, in order to calculate a total electrical charge drawn from and delivered to the battery. Because coulomb counters continuously integrate, extremely low direct-current (DC) offset in coulomb counter circuitry is desired. FIG. 1 illustrates a block diagram of an example coulomb counter, as is known in the art. As shown in FIG. 1, a coulomb counter 1 may include a sense resistor 2 for measuring a sense voltage VSNS which is indicative of an electrical current ISNS flowing through the sense resistor. For example, electrical current ISNS may comprise a current drawn from a battery. As also shown in FIG. 1, coulomb counter 1 may include an integrator 4 implemented in part with an amplifier 6, such integrator 4 configured to integrate electrical current ISNS over time, providing an indication of net electrical charge that has flowed through sense resistor 2. Thus, if sense resistor 2 is coupled to the output of a battery, coulomb counter 1 may calculate a net electrical charge drawn from the battery. As also shown in FIG. 1, coulomb counter 1 may implement both system-level chopping using chopping blocks 8 and block-level chopping within integrator 4, using chopping blocks 10. Block-level chopping blocks 10 may operate at a first chopping frequency (e.g., one-half the sampling frequency fs of coulomb counter 1) to reduce DC offset and inverse frequency noise (also known as 1/f noise) of amplifier 6, and system-level chopping blocks 8 may operate at a second chopping frequency (e.g., fs/512) to further minimize the residual DC offset for coulomb counter 1. For better clarity, coulomb counter 1 depicted in FIG. 1 may be represented as a signal processing block diagram as shown in FIG. 2. As shown in FIG. 2, system-level chopping blocks 8 are represented as mixers 12, each having a chopping frequency fchsys, at the input and output of a sigma-delta analog to digital converter (ADC) 14 that comprises integrator 4 and a three-level quantizer 16. Block-level chopping blocks 10 are not depicted in FIG. 2. Coulomb counter 1 as depicted in FIGS. 1 and 2 employs first-order sigma-delta modulation. A disadvantage of such approach is that the minimum charge resolution using first-order sigma-delta modulation may be limited to higher than that which may be desirable. One improvement over coulomb counter 1 depicted in FIGS. 1 and 2 is that set forth in U.S. Pat. No. 11,777,516, in which slow-running switches are placed before and after an integrator of a sigma-delta modulator in order to undo system level chopping of an integrating capacitor of the integrator. However, one disadvantage of such approach is that the presence of choppers before and after the integrator introduces signal error. SUMMARY In accordance with the teachings of the present disclosure, certain disadvantages and problems associated with existing sensor systems may be reduced or eliminated. In accordance with embodiments of the present disclosure, a signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity. The sensor readout channel may include a sigma-delta modulator having a modulator input and a modulator output, first system-level chopping switches located at the modulator input, an auxiliary path comprising an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the sigma-delta modulator, second system-level chopping switches locate