US-12627317-B2 - Data encoding, data decoding, a semiconductor apparatus and a semiconductor system using the same

Abstract

A data encoding method encodes eleven binary bits as seven symbols. The data encoding method generates a check signal based on first to fourth bits. The data encoding method includes encoding first to fifth bits to generate first to third symbols. The method includes encoding sixth to eighth bits to generate fourth and fifth symbols. The method also includes encoding ninth to eleventh bits to generate sixth and seventh symbols, when the check signal has a first logic level.

Inventors

• Hyun Su Park

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260512

Application Date

20240606

Priority Date

20231213

Claims (20)

1. 1 . A data encoding method, the method comprising: setting first to fifth bits as a first bit group, sixth to eighth bits as a second bit group, and ninth to eleventh bits as a third bit group; generating a check signal based on the first to fourth bits; and encoding the first to third bit groups based on the check signal and the fifth bit to generate first to seventh symbols, wherein when the check signal is at a first logic level, the first to third symbols are generated by encoding the first bit group, the fourth and fifth symbols are generated by encoding the second bit group, and the sixth and seventh symbols are generated by encoding the third bit group.
2. 2 . The method of claim 1 , wherein the third to fifth bits of the first bit group, the sixth to eighth bits of the second bit group, and the ninth to eleventh bits of the third bit group are encoded based on the same mapping table.
3. 3 . The method of claim 1 , wherein when the check signal is at a second logic level and the fifth bit is at the first logic level, the fourth and fifth symbols are masked, and when the check signal is at the second logic level and the fifth bit is at the second logic level, the sixth and seventh symbols are masked.
4. 4 . The method of claim 1 , wherein when the check signal is at a second logic level and the fifth bit has a logic level of the first logic level or the second logic level, the third and fourth bits are encoded as the first symbol, the second bit group is encoded as the second and third symbols, the fourth and fifth symbols having a fixed value are generated, and the third bit group is encoded as the sixth and seventh symbols.
5. 5 . The method of claim 4 , wherein when the check signal is at a second logic level and the fifth bit has the other logic level from the first logic level and the second logic level, the third and fourth bits are encoded as the first symbol, the second bit group is encoded as the second and third symbols, the third bit group is encoded as the fourth and fifth symbols, and the sixth and seventh symbols having a fixed value are generated.
6. 6 . A data decoding method, the method comprising: setting first to third symbols as a first symbol group, fourth and fifth symbols as a second symbol group, and sixth and seventh symbols as a third symbol group; generating a check signal based on least significant bits of the fourth to seventh symbols; and decoding the first to third symbol groups based on the check signal and the least significant bits of the sixth and seventh symbols to generate first to eleventh bits, wherein when the check signal is at a first logic level, the first symbol group is decoded as the first to fifth bits, the second symbol group is decoded as the sixth to eighth bits, and the third symbol group is decoded as the ninth to eleventh bits.
7. 7 . The method of claim 6 , wherein the second and third symbols of the first symbol group, the fourth and fifth symbols of the second symbol group, and the sixth and seventh symbols of the third symbol group are decoded based on the same mapping table.
8. 8 . The method of claim 6 , wherein when the check signal is at a second logic level, the first and second bits having the second logic level are generated.
9. 9 . The method of claim 6 , wherein when the check signal is at a second logic level and at least one of the least significant bits of the sixth and seventh symbols is at the second logic level, the fifth bit having a logic level of one of the first logic level and the second logic level is generated, and when the check signal is at the second logic level and the least significant bits of the sixth and seventh symbols are at the first logic level, the fifth bit having a logic level of the other from the first logic level and the second logic level is generated.
10. 10 . The method of claim 6 , wherein when the check signal is at a second logic level and at least one of the least significant bits of the sixth and seventh symbols is at the second logic level, the first and second bits having the second logic level are generated, the fifth bit having the first logic level is generated, the first symbol is decoded as the third and fourth bits, the first symbol group is decoded as first to fifth decoding bits, and the third to fifth decoding bits are provided as the sixth to eighth bits, and the third symbol group is decoded as the ninth to eleventh bits.
11. 11 . The method of claim 6 , wherein when the check signal is at a second logic level and the least significant bits of the sixth and seventh symbols are at the first logic level, the first bit, the second bit, and the fifth bit having the second logic level are generated, the first symbol is decoded as the third and fourth bits, the first symbol group is decoded as first to fifth decoding bits, and the third to fifth decoding bits are provided as the sixth to eighth bits, and the second symbol group is decoded as the ninth to eleventh bits.
12. 12 . A data encoding circuit comprising: a first encoding circuit configured to encode first to fifth bits to generate first to sixth encoding bits, configured to output one of the first and second encoding bits and the third and fourth encoding bits as a first symbol based on a check signal, and configured to output the third to sixth encoding bits and seventh to tenth encoding bits as a second symbol and a third symbol based on the check signal; a second encoding circuit configured to encode sixth to eighth bits to generate the seventh to tenth encoding bits, and configured to output one of the seventh to tenth encoding bits, eleventh to fourteenth encoding bits, and a fixed value as a fourth symbol and a fifth symbol based on the check signal and the fifth bit; a third encoding circuit configured to encode ninth to eleventh bits to generate the eleventh to fourteenth encoding bits, and configured to output one of the eleventh to fourteenth encoding bits and the fixed value as a sixth symbol and a seventh symbol based on a selection signal; a check logic circuit configured to generate the check signal based on the first to fourth bits; and a selection logic circuit configured to generate the selection signal based on the check signal and the fifth bit.
13. 13 . The data encoding circuit of claim 12 , wherein the first encoding circuit comprises: a first encoder configured to encode the first to fifth bits to generate the first to sixth encoding bits; a first selection circuit configured to output the first and second encoding bits as the first symbol when the check signal is at a first logic level, and configured to output the third and fourth encoding bits as the first symbol when the check signal is at a second logic level; and a second selection circuit configured to output the third to sixth encoding bits as the second and third symbols when the check signal is at the first logic level, and configured to output the seventh to tenth encoding bits as the second and third symbols when the check signal is at the second logic level.
14. 14 . The data encoding circuit of claim 13 , wherein the first encoder comprises a 5b3s encoder that encodes the first to fifth bits as the first to third symbols.
15. 15 . The data encoding circuit of claim 13 , wherein the second encoding circuit comprises: a second encoder configured to encode the sixth to eighth bits to generate the seventh to tenth encoding bits; and a third selection circuit configured to output the seventh to tenth encoding bits as the fourth and fifth symbols when the check signal is at the first logic level, configured to output the fixed value as the fourth and fifth symbols when the check signal is at the second logic level and the fifth bit is at the first logic level, and configured to output the eleventh to fourteenth encoding bits as the fourth and fifth symbols when the check signal and the fifth bit are at the second logic level.
16. 16 . The data encoding circuit of claim 15 , wherein the second encoder comprises a 3b2s encoder that encodes the sixth to eighth bits as the seventh to tenth encoding bits.
17. 17 . The data encoding circuit of claim 13 , wherein the third encoding circuit comprises: a third encoder configured to encode the ninth to eleventh bits to generate the eleventh to fourteenth encoding bits; and a fourth selection circuit configured to output the eleventh to fourteenth encoding bits as the sixth and seventh symbols when the selection signal is at the first logic level, and configured to output the fixed value as the sixth and seventh symbols when the selection signal is at the second logic level.
18. 18 . The data encoding circuit of claim 17 , wherein the third encoder comprises a 3b2s encoder that encodes the ninth to eleventh bits as the eleventh to fourteenth encoding bits.
19. 19 . The data encoding circuit of claim 13 , wherein the check logic circuit is configured to generate the check signal having the first logic level when at least one of the first and second bits is at the first logic level or when the third and fourth bits are at the first logic level, and configured to generate the check signal having the second logic level when the first and second bits are at the second logic level and at least one of the third and fourth bits is at the second logic level.
20. 20 . The data encoding circuit of claim 13 , wherein the selection logic circuit is configured to generate the selection signal having the first logic level when one of the check signal and the fifth bit is at the first logic level, and configured to generate the selection signal having the second logic level when the check signal and the fourth bit are at the second logic level.

Description

CROSS-REFERENCES TO RELATED APPLICATION The present application claims priority under 35 U.S.C. § 119 (a) to Korean patent application number 10-2023-0180904 filed on Dec. 13, 2023, in the Korean Intellectual Property Office, which application is incorporated herein by reference in its entirety. BACKGROUND 1. Technical Field Various embodiments generally relate to integrated circuit technology, and, more particularly, to data encoding, data decoding, and a semiconductor apparatus and a semiconductor system using the same. 2. Related Art An electronic device includes many electronic elements. A computer system, for example, includes many semiconductor apparatuses each configured by a semiconductor. The semiconductor apparatuses constituting a computer system may communicate with each other by transmitting and receiving clock signals and data. The semiconductor apparatuses may be connected to other semiconductor apparatus through a data bus and may transmit and receive signals having information corresponding to the data through a signal bus. Typically, a Non-Return-to-Zero (NRZ) signal having a logic level of 0 or 1 may be transmitted through the data bus. However, to transmit more information with one signal transmission, a multi-level signal transmission method using Pulse Amplitude Modulation (PAM) is being used. The multi-level signal transmission method can transmit two or more bits of digital information as one analog signal by subdividing a level of an analog voltage transmitted through the signal bus. To use the multi-level signal transmission method, the semiconductor apparatuses may have a transmitter circuit that encodes a plurality of bits of data to generate a plurality of symbols, and transmits a multi-level signal having three or more voltage levels based on each symbol to the data bus. Further, the semiconductor apparatuses may have a receiver circuit for receiving the multi-level signal transmitted through the data bus to restore the symbols, and for decoding the symbols to generate the plurality of bits of data. SUMMARY In an embodiment, a data encoding method may include setting first to fifth bits as a first bit group, sixth to eighth bits as a second bit group, and ninth to eleventh bits as a third bit group. The method may include generating a check signal based on the first to fourth bits. And the method may include encoding the first to third bit groups based on the check signal and the fifth bit to generate first to seventh symbols. In an embodiment, when the check signal is at a first logic level, the first to third symbols may be generated by encoding the first bit group, the fourth and fifth symbols may be generated by encoding the second bit group, and the sixth and seventh symbols may be generated by encoding the third bit group. In an embodiment, a data decoding method may include setting first to third symbols as a first symbol group, fourth and fifth symbols as a second symbol group, and sixth and seventh symbols as a third symbol group. The method may include generating a check signal based on least significant bits of the fourth to seventh symbols. And the method may include decoding the first to third symbol groups based on the check signal and the least significant bits of the sixth and seventh symbols to generate first to eleventh bits. In an embodiment, when the check signal is at a first logic level, the first symbol group may be decoded as the first to fifth bits, the second symbol group may be decoded as the sixth to eighth bits, and the third symbol group may be decoded as the ninth to eleventh bits. In an embodiment, a data encoding circuit may include a first encoding circuit, a second encoding circuit, a third encoding circuit, a check logic circuit, and a selection logic circuit. The first encoding circuit may be configured to encode first to fifth bits to generate first to sixth encoding bits, may be configured to output one of the first and second encoding bits and the third and fourth encoding bits as a first symbol based on a check signal, and may be configured to output the third to sixth encoding bits and seventh to tenth encoding bits as a second symbol and a third symbol based on the check signal. The second encoding circuit may be configured to encode sixth to eighth bits to generate the seventh to tenth encoding bits, and may be configured to output one of the seventh to tenth encoding bits, eleventh to fourteenth encoding bits, and a fixed value as a fourth symbol and a fifth symbol based on the check signal and the fifth bit. The third encoding circuit may be configured to encode ninth to eleventh bits to generate the eleventh to fourteenth encoding bits, and may be configured to output one of the eleventh to fourteenth encoding bits and the fixed value as a sixth symbol and a seventh symbol based on a selection signal. The check logic circuit may be configured to generate the check signal based on the first to fourth bits. The selection logic circui