US-12627390-B2 - Providing arbitrarily long timer from shorter underlying hardware counter

Abstract

Systems and methods for extending an original bit length counter maintained by hardware of a network device to generate an extended length timestamp of a longer bit length are disclosed. The extension of the original bit length counter is based on a rollover counter, where the rollover counter is incremented based on the detection of rollovers of the original bit length counter.

Inventors

• Yin Chen
• Andrew Peter Maxwell
• Avininderpal Singh Grewal
• Jeff Chan

Assignees

• ARISTA NETWORKS, INC.

Dates

Publication Date

20260512

Application Date

20230811

Claims (20)

1. 1 . A network device, comprising: processing circuitry, including: a switching circuit including a time of day (TOD) counter of a first bit length; and an extended timestamp module adapted for generating a value for an extended bit length TOD counter for a second bit length greater than the first bit length by: maintaining a rollover counter, wherein a value of the rollover counter is incremented based on a detection of a rollover of the TOD counter and the rollover counter has a second bit length; obtaining a first value of the TOD counter from the switching circuit of the network device, wherein the extended timestamp module generates the value for an extended bit length TOD counter based on the value of the rollover counter and the obtained value of the TOD counter, wherein the extended bit length TOD counter has a third bit length that is the sum of the first bit length and the second bit length.
2. 2 . The network device of claim 1 , wherein the extended timestamp module is executing in kernel space of an operating system executing on the processing circuitry of the network device.
3. 3 . The network device of claim 1 , wherein the rollover counter is incremented based on a comparison of the obtained first value of the TOD counter and a previous value of the TOD counter.
4. 4 . The network device of claim 1 , wherein the extended timestamp module provides an interface for a kernel process and an interface for a user space application.
5. 5 . The network device of claim 4 , wherein the first value of the TOD counter is obtained when a request for the value for the extended bit length TOD counter is received through the interface for the kernel process or the interface for the user space application.
6. 6 . The network device of claim 5 , wherein the detection of the rollover of the TOD counter is performed when the request for the value for the extended bit length TOD counter is received through the interface for the kernel process or the interface for the user space application.
7. 7 . A method for increasing precision of a hardware counter, comprising: maintaining a rollover counter, wherein the rollover counter is incremented based on a detection of a rollover of a first counter in hardware of a computing device, and wherein the first counter is a time of day (TOD) counter having a first bit length; obtaining a first value of the first counter from the hardware of the computing device; and generating a value for an extended bit length TOD counter based on a value of the rollover counter and the obtained first value of the first counter, wherein the extended bit length TOD counter has a second bit length greater than the first bit length.
8. 8 . The method of claim 7 , wherein the detection of the rollover of the first counter comprises: obtaining a second value of the first counter from the hardware of the computing device; determining if the obtained second value of the first counter is less than a previously obtained value of the first counter; and detecting the rollover when the obtained second value is less than the previously obtained value.
9. 9 . The method of claim 8 , wherein the first obtained value and the second obtained value are the same obtained value.
10. 10 . The method of claim 8 , wherein the second value of the first counter is obtained based on reception of an interrupt from the hardware.
11. 11 . The method of claim 8 , wherein the second value of the first counter is obtained based on expiration of a rollover timer associated with the rollover counter.
12. 12 . The method of claim 11 , wherein the rollover timer has a rollover period less than a rollover time of the first counter.
13. 13 . The method of claim 7 , wherein a bit length of the rollover counter corresponds to a difference between the second bit length and the first bit length.
14. 14 . The method of claim 7 , wherein generating the value for the extended bit length counter comprises left shifting the value of the rollover counter by a number of bits corresponding to the first bit length and adding the first value of the first counter to a result of the left shifting of the value for the rollover counter.
15. 15 . A non-transitory computer readable medium, comprising instructions for: incrementing a rollover counter based on a detection of a rollover of a first counter in hardware of a computing device, and wherein the first counter is a time of day (TOD) counter having a first bit length; obtaining a first value of the first counter from the hardware of the computing device; and generating a value for an extended bit length TOD counter based on a value of the rollover counter and the obtained first value of the first counter, wherein the extended bit length TOD counter has a second bit length greater than the first bit length.
16. 16 . The non-transitory computer readable medium of claim 15 , wherein the instructions are executable in kernel space of the computing device.
17. 17 . The non-transitory computer readable medium of claim 15 , wherein the instructions are further for detecting the rollover when the obtained first value of the first counter is less than a previously obtained value of the first counter.
18. 18 . The non-transitory computer readable medium of claim 15 , wherein the first value is obtained in response to receiving a request for the extended bit length counter.
19. 19 . The non-transitory computer readable medium of claim 15 , wherein the first value is obtained based on expiration of a rollover timer.
20. 20 . The non-transitory computer readable medium of claim 19 , wherein the rollover timer has a rollover period less than a rollover time of the first counter.

Description

BACKGROUND Oftentimes in various computing applications precision timing (e.g., sub-microsecond) is required. To aid in the implementation of such precision timing applications, hardware timers may be provided in Application Specific Integrated Circuits (ASICs) or other types of processors, such as Central Processing Units (CPUs), microprocessors, Graphics Processing Units (GPUs), etc. These hardware timers may, for example, be Time of Day (TOD) counters or the like. As such, these hardware timers may be used for providing timestamps for various uses. These timestamps may thus be heavily utilized in certain contexts or environments where timing or synchronization is of utmost importance. One such context is networking, where the implementation and use of network devices (e.g., hardware or software utilized in a network, collectively referred to as network devices or elements interchangeably) may depend on accurate timing. Accordingly, timestamps may be used for various functions in the operation of computing devices, including network devices or the like. For example, in the context of network devices the implementation of certain protocols involved with the synchronization of timing between network elements in a network environment may require such timestamps. For example, the IEEE 1588v2 Precision Time Protocol (PTP) defines a packet-based time synchronization method that provides frequency, phase, and TOD information with sub-microsecond accuracy. While certain hardware may provide counters that can be used for generating the timestamps needed in these contexts, in certain cases longer time values than are provided in the hardware may be desired. Specifically, the hardware counters may be of shorter bit length than the length of the time value desired. This size discrepancy leads to problems as these hardware counters may not simply be expanded to the length desired. As but one problem, shorter length hardware counters may reset at some interval (e.g., determined by their length and timing resolution). Thus, a longer length time value may not simply be determined directly from a shorter hardware counter, as that hardware counter may have been reset. What is desired, therefore, are simple mechanisms that allow the extension of shorter timestamp values that are available from underlying hardware. BRIEF DESCRIPTION OF THE DRAWINGS The drawings accompanying and forming part of this specification are included to depict certain aspects of the disclosure. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. A more complete understanding of the disclosure and the advantages thereof may be acquired by referring to the following description, taken in conjunction with the accompanying drawings in which like reference numbers indicate like features. FIG. 1 is a block diagram depicting one embodiment of a general architecture of a network device for generating an extended bit length counter. FIG. 2 is a block diagram depicting one embodiment of a network device for generating an extended bit length counter. FIG. 3 is a block diagram depicting one embodiment of a network device for generating an extended bit length counter. FIG. 4 is a block diagram depicting one embodiment of a network device for generating and using an extended bit length counter in the context of a PTP implementation on the network device. FIG. 5 is a flow diagram for one embodiment of a method for generating an extended bit length counter. DETAILED DESCRIPTION As discussed, precision timing is required in many computing applications. One context where precision timing is especially important is networking, where the implementation and use of network devices may depend on accurate timing. Hardware timers (e.g., in ASICs, CPUs, etc.) referred to herein generally as Time of Day (TOD) counters, may be used for providing timestamps for use in applications utilizing such precision timing. To illustrate, timestamps may be used in the implementation of certain protocols involved with the synchronization of timing between network elements in a network environment. For example, the IEEE 1588v2 Precision Time Protocol (PTP) defines a packet-based time synchronization method that provides frequency, phase, and TOD information with sub-microsecond accuracy. Each PTP network element maintains a PTP free-running TOD counter used as a basis for generating recovered clock signals and computing latencies, offsets, or drift rates. The free-running counter can be associated with a local system clock on a network device asynchronously to the clocks maintained by other members of the PTP network. Correction factors may be applied to the free-running clock in order to arrive at a local time value that is synchronized to a master clock. Alternatively, an implementation of PTP may involve correcting the TOD counter maintained in hardware to eliminate timing or other errors. As discussed, certain hardware may provide counters