US-12627532-B1 - Techniques to perform channel estimation

Abstract

Apparatuses, systems, and techniques to perform channel estimation. In at least one embodiment, a processor includes one or more circuits to perform channel estimation corresponding to one or more wireless signals without using a reference signal.

Inventors

• Shaoran Li
• Yan Huang
• James Hansen Delfeld
• Christopher Hans Dick

Assignees

• NVIDIA CORPORATION

Dates

Publication Date

20260512

Application Date

20220303

Claims (20)

1. 1 . One or more processors, comprising circuitry to: generate one or more Fifth Generation (5G) channel estimation values based, at least in part, on varying information encoded into one or more corresponding 5G signals by at least performing coherent signal combination without a reference signal.
2. 2 . The one or more processors of claim 1 , wherein the varying information includes multiple different possibilities of information encoded by the one or more corresponding 5G signals.
3. 3 . The one or more processors of claim 1 , wherein the circuitry is to further perform the coherent signal combination corresponding to a wireless signal of the one or more corresponding 5G signals received by multiple antennas based, at least in part, on the 5G channel estimation values.
4. 4 . The one or more processors of claim 1 , wherein the circuitry is to; further perform the coherent combination corresponding to a wireless signal of the one or more corresponding 5G signals received by multiple antennas based, at least in part, on the 5G channel estimation values; and identify a cyclic shift of a base sequence based, at least in part, on the coherent combination.
5. 5 . The one or more processors of claim 1 , wherein the circuitry is to generate the 5G channel estimation values based, at least in part, on one or more neural networks.
6. 6 . The one or more processors of claim 1 , wherein the circuitry is to identify a cyclic shift value of a received wireless signal of the one or more corresponding 5G signals transmitted by a user equipment device based, at least in part, on a base sequence corresponding to the user equipment device.
7. 7 . The one or more processors of claim 1 , wherein the circuitry is to: further perform the coherent combination corresponding to a wireless signal received by multiple antennas based, at least in part, on the 5G channel estimation values; identify a cyclic shift of a base sequence based, at least in part, on the coherent combination; and identify one or more cyclic shift values based, at least in part, on the cyclic shift.
8. 8 . The one or more processors of claim 1 , wherein the circuitry is to identify information corresponding to a physical uplink control channel (PUCCH) format zero signal or a physical random access channel (PRACH) signal received from a user equipment device based, at least in part, on the 5G channel estimation values.
9. 9 . A system, comprising: one or more processors to generate one or more Fifth Generation (5G) channel estimation values based, at least in part, on varying information encoded into one or more corresponding 5G signals by at least performing coherent signal combination without a reference signal; and one or more memories to store the one or more 5G channel estimation values.
10. 10 . The system of claim 9 , wherein the varying information includes multiple different possibilities of information encoded by the one or more corresponding 5G signals.
11. 11 . The system of claim 9 , wherein the one or more processors are to perform the coherent combination corresponding to a wireless signal of the one or more corresponding 5G signals received by multiple antennas based, at least in part, on the 5G channel estimation values.
12. 12 . The system of claim 9 , wherein the one or more processors are to generate the 5G channel estimation values based, at least in part, on one or more neural networks.
13. 13 . The system of claim 9 , wherein the one or more processors are to identify a cyclic shift value of a received wireless signal of the one or more corresponding 5G signals based, at least in part, on a base sequence and the 5G channel estimation values.
14. 14 . The system of claim 9 , wherein the one or more processors are to perform the coherent combination corresponding to a wireless signal of the one or more corresponding 5G signals received by multiple antennas based, at least in part, on the 5G channel estimation values and one or more of: maximum ratio combining (MRC), zero-forcing (ZF), or minimum mean square error (MMSE) detection.
15. 15 . The system of claim 9 , wherein the one or more processors are to identify uplink control information corresponding to a received wireless signal of the one or more corresponding 5G signals transmitted by a user equipment device based, at least in part, on the 5G channel estimation values.
16. 16 . A non-transitory machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least: generate one or more Fifth Generation (5G) channel estimation values based, at least in part, on varying information encoded into one or more corresponding 5G signals by at least performing coherent signal combination without a reference signal.
17. 17 . The non-transitory machine-readable medium of claim 16 , wherein the instructions, which if performed by the one or more processors, cause the one or more processors to identify a cyclic shift value of a physical uplink control channel (PUCCH) format 0 signal based, at least in part, on the channel estimation values.
18. 18 . The non-transitory machine-readable medium of claim 16 , wherein the instructions, which if performed by the one or more processors, cause the one or more processors to perform the coherent combination corresponding to a wireless signal of the one or more corresponding 5G signals received by multiple antennas based, at least in part, on the 5G channel estimation values.
19. 19 . The non-transitory machine-readable medium of claim 16 , wherein the instructions, which if performed by the one or more processors, cause the one or more processors to generate the 5G channel estimation values based, at least in part, on one or more of performing: one or more least square calculations, or one or more minimum mean square error calculations.
20. 20 . The non-transitory machine-readable medium of claim 16 , wherein the instructions, which if performed by the one or more processors, cause the one or more processors to identify a cyclic shift value of a received wireless signal of the one or more corresponding 5G signals based, at least in part, on the 5G channel estimation values.

Description

FIELD OF INVENTION At least one embodiment pertains to processing resources used to perform channel estimation and signal detection for wireless communications signals. For example, at least one embodiment pertains to parallel processors or computing systems that use one or more neural networks to detect received signals according to various novel techniques described herein. BACKGROUND Processing wireless communications signals and data can use significant computing resources and time. Approaches to detecting wireless communications signals and data can be improved. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram that illustrates a system, according to at least one embodiment; FIG. 2 is a block diagram that illustrates a system to perform channel estimation, according to at least one embodiment; FIG. 3 is a block diagram that illustrates coherent signal detection, according to at least one embodiment; FIG. 4 is a block diagram that illustrates signal detection using maximum ratio combining, according to at least one embodiment; FIG. 5 is a block diagram that illustrates signal detection using a neural network, according to at least one embodiment; FIG. 6 is a block diagram that illustrates a deep neural network operation, according to at least one embodiment; FIG. 7 is a block diagram that illustrates signal detection using a neural network, according to at least one embodiment; FIG. 8 is a block diagram that illustrates a deep neural network operation, according to at least one embodiment; FIG. 9 is a flowchart of a technique of performing coherent detection, according to at least one embodiment; FIG. 10 is a flowchart of a technique of performing signal detection, according to at least one embodiment; FIG. 11 illustrates an example data center system, according to at least one embodiment; FIG. 12A illustrates an example of an autonomous vehicle, according to at least one embodiment; FIG. 12B illustrates an example of camera locations and fields of view for the autonomous vehicle of FIG. 12A, according to at least one embodiment; FIG. 12C is a block diagram illustrating an example system architecture for the autonomous vehicle of FIG. 12A, according to at least one embodiment; FIG. 12D is a diagram illustrating a system for communication between cloud-based server(s) and the autonomous vehicle of FIG. 12A, according to at least one embodiment; FIG. 13 is a block diagram illustrating a computer system, according to at least one embodiment; FIG. 14 is a block diagram illustrating computer system, according to at least one embodiment; FIG. 15 illustrates a computer system, according to at least one embodiment; FIG. 16 illustrates a computer system, according to at least one embodiment; FIG. 17A illustrates a computer system, according to at least one embodiment; FIG. 17B illustrates a computer system, according to at least one embodiment; FIG. 17C illustrates a computer system, according to at least one embodiment; FIG. 17D illustrates a computer system, according to at least one embodiment; FIGS. 17E and 17F illustrate a shared programming model, according to at least one embodiment; FIG. 18 illustrates exemplary integrated circuits and associated graphics processors, according to at least one embodiment; FIGS. 19A and 19B illustrate exemplary integrated circuits and associated graphics processors, according to at least one embodiment; FIGS. 20A and 20B illustrate additional exemplary graphics processor logic according to at least one embodiment; FIG. 21 illustrates a computer system, according to at least one embodiment; FIG. 22A illustrates a parallel processor, according to at least one embodiment; FIG. 22B illustrates a partition unit, according to at least one embodiment; FIG. 22C illustrates a processing cluster, according to at least one embodiment; FIG. 22D illustrates a graphics multiprocessor, according to at least one embodiment; FIG. 23 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment; FIG. 24 illustrates a graphics processor, according to at least one embodiment; FIG. 25 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment; FIG. 26 illustrates at least portions of a graphics processor, according to one or more embodiments; FIG. 27 illustrates at least portions of a graphics processor, according to one or more embodiments; FIG. 28 illustrates at least portions of a graphics processor, according to one or more embodiments; FIG. 29 is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment; FIG. 30 is a block diagram of at least portions of a graphics processor core, according to at least one embodiment; FIGS. 31A and 31B illustrate thread execution logic including an array of processing elements of a graphics processor core according to at least one embodiment; FIG. 32 illustrates a parallel processing unit (“PPU”), a