US-12627537-B2 - Minimum euclidean distance finder and operating method thereof

Abstract

An operating method of a modem chip includes receiving a first Euclidean distance (ED) set including an ED of first symbol vector candidates, comparing magnitudes of the EDs of the first ED set, calculating each of a first minimum ED corresponding to a bit value of a first bit being 1 and a second minimum ED corresponding to the bit value of the first bit being 0, the first bit being from among a plurality of bits of a plurality of layers of the transmission symbol, based on first index information including results of the comparing the magnitudes of the EDs of the first ED set, updating the first minimum ED and the second minimum ED with a smallest first minimum ED and a smallest second minimum ED, respectively, and detecting the transmission symbol based on the updated first minimum ED and the updated second minimum ED.

Inventors

• Jungyeong SEO
• Jooyeol Yang

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20240322

Priority Date

20230331

Claims (20)

1. 1 . An operating method of a modem chip, the operating method comprising: receiving a first Euclidean distance (ED) set including an ED of each of n first symbol vector candidates from among a plurality of symbol vector candidates for a transmission symbol, wherein n is a natural number of 2 or greater; comparing magnitudes of each potential combination of two EDs of the first ED set to obtain first index information including results of the comparing the magnitudes of the EDs of the first ED set; for each bit in the transmission symbol: calculating each of a first minimum ED corresponding to a bit value of a corresponding bit being 1 and a second minimum ED corresponding to the bit value of the corresponding bit being 0, based on the first index information; updating the first minimum ED and the second minimum ED with a smallest first minimum ED and a smallest second minimum ED, respectively; and detecting the transmission symbol based on the updated first minimum ED and the updated second minimum ED for each bit in the transmission symbol.
2. 2 . The operating method of claim 1 , wherein the calculating comprises: receiving bit values of the n first symbol vector candidates corresponding to the corresponding bit; and calculating the first minimum ED and the second minimum ED, based on the first index information and bit values of the n first symbol vector candidates corresponding to the corresponding bit.
3. 3 . The operating method of claim 2 , wherein the calculating further comprises: dividing the first ED set into a second ED set having EDs corresponding to the bit values of the corresponding bit of the n first symbol vector candidates being 1 and a third ED set having EDs corresponding to the bit values of the corresponding bit of the n first symbol vector candidates being 0, based on the first index information; calculating the smallest first minimum ED from the second ED set based on the first index information; and calculating the smallest second minimum ED from the third ED set based on the first index information.
4. 4 . The operating method of claim 3 , wherein calculating the first minimum ED comprises: selecting a first index indicating a smallest ED from among the EDs of the second ED set, based on the first index information; and converting the first index into the first minimum ED.
5. 5 . The operating method of claim 3 , wherein calculating the second minimum ED comprises: selecting a second index indicating a smallest ED from among the EDs of the third ED set, based on the first index information; and converting the second index into the second minimum ED.
6. 6 . The operating method of claim 1 , wherein the updating comprises: receiving a fourth ED set including an ED of each of n second symbol vector candidates from among the plurality of symbol vector candidates for the transmission symbol; comparing magnitudes of the EDs of the fourth ED set; calculating each of a third minimum ED corresponding to the bit value of the corresponding bit being 1 and a fourth minimum ED corresponding to the bit value of the corresponding bit being 0, based on second index information including results of the comparing the magnitudes of the EDs of the fourth ED set; and updating the first minimum ED to a smaller value from among the first minimum ED and the third minimum ED; and updating the second minimum ED to a smaller value from among the second minimum ED and the fourth minimum ED.
7. 7 . The operating method of claim 6 , wherein the n first symbol vector candidates are different from the n second symbol vector candidates.
8. 8 . The operating method of claim 1 , further comprising calculating a log likelihood ratio (LLR) for the corresponding bit, based on the first minimum ED and the second minimum ED.
9. 9 . A modem chip comprising: a common comparator configured to receive a first Euclidean distance (ED) set including an ED of each of n first symbol vector candidates from among a plurality of symbol vector candidates for a transmission symbol, wherein n is a natural number of 2 or greater, compare magnitudes of each potential combination of two EDs of the first ED set, and output first index information including results of comparing the magnitudes of the EDs of the first ED set; and an index-based ED finder configured to, for each bit in the transmission symbol: calculate each of a first minimum ED corresponding to a bit value of a corresponding bit being 1 and a second minimum ED of the bit value of the corresponding bit being 0, based on the first index information, and update the first minimum ED and the second minimum ED with a smallest first minimum ED and a smallest second minimum ED, respectively.
10. 10 . The modem chip of claim 9 , wherein the index-based ED finder is further configured to receive bit values of the n first symbol vector candidates corresponding to the corresponding bit, and calculate each of the first minimum ED and the second minimum ED, based on the first index information and the bit values of the n first symbol vector candidates corresponding to the corresponding bit.
11. 11 . The modem chip of claim 9 , wherein the index-based ED finder is further configured to: divide the first ED set into a second ED set having EDs corresponding to bit values for the corresponding bit of the n first symbol vector candidates being 1 and a third ED set having EDS corresponding to the bit values for the corresponding bit of the n first symbol vector candidates being 0, based on the first index information; calculate the smallest first minimum ED from the second ED set based on the first index information; and calculate the smallest second minimum ED from the third ED set based on the first index information.
12. 12 . The modem chip of claim 11 , wherein the index-based ED finder is further configured to: select a first index indicating a smallest ED from among the EDs of the second ED set, based on the first index information; and convert the first index into the first minimum ED.
13. 13 . The modem chip of claim 11 , wherein the index-based ED finder is further configured to: select a second index indicating a smallest ED from among the EDs of the third ED set, based on the first index information; and convert the second index into the second minimum ED.
14. 14 . The modem chip of claim 9 , wherein the common comparator is further configured to receive a fourth ED set including an ED of each of n second symbol vector candidates from among the plurality of symbol vector candidates for the transmission symbol, compare magnitudes of the EDs of the fourth ED set, and output second index information including results of the comparison of the magnitudes of the EDs of the fourth ED set, and wherein the index-based ED finder is further configured to calculate each of a third minimum ED corresponding to the bit value of the corresponding bit being 1 and a fourth minimum ED corresponding to the bit value of the corresponding bit being 0, based on the second index information, update the first minimum ED to a smaller value from among the first minimum ED and the third minimum ED, and update the second minimum ED to a smaller value from among the second minimum ED and the fourth minimum ED.
15. 15 . The modem chip of claim 14 , wherein the n first symbol vector candidates are different from the n second symbol vector candidates.
16. 16 . The modem chip of claim 9 , further comprising a log likelihood ratio (LLR) calculation circuit configured to calculate an LLR for the corresponding first-bit, based on the first minimum ED and the second minimum ED.
17. 17 . The modem chip of claim 9 , further comprising a symbol detector configured to detect the transmission symbol based on the updated first minimum ED and the updated second minimum ED.
18. 18 . A minimum Euclidean distance (ED) finder comprising: a common comparator configured to receive a first ED set including an ED of each of four first symbol vector candidates from among a plurality of symbol vector candidates for a transmission symbol, compare magnitudes of the EDs of the first ED set, and output first index information and second index information, the first index information comprising a first magnitude comparison result of a first pair of EDs in the first ED set and a second magnitude comparison result of a second pair of EDs in the first ED set, and the second index information comprising magnitude comparison results of remaining pairs of EDs included in the first ED set; a first classifier configured to receive the first index information and bit values of the first pair of EDs for a first bit that is one of a plurality of bits of a plurality of layers of the transmission symbol, and output a first index related to the bit values of the first bit being 1 and a second index related to the bit values of the first bit being 0; a second classifier configured to receive the first index information and bit values of the second pair of EDs for the first bit, and output a third index related to the bit values of the second pair of EDs for the first bit being 1 and a fourth index related to the bit values of the second pair of EDs for the first bit being 0; a first index-based comparator configured to receive the second index information, the first index, and the third index, and output a fifth index indicating a first minimum ED corresponding to a bit value being 1 for the first bit; a second index-based comparator configured to receive the second index information, the second index, and the fourth index, and output a sixth index indicating a second minimum ED corresponding to the bit value being 0 for the first bit; a converter configured to convert the fifth index into the first minimum ED and the sixth index into the second minimum ED; and an iterative comparison circuit configured to update the first minimum ED and the second minimum ED.
19. 19 . The minimum ED finder of claim 18 , wherein the first pair of EDs is different from the second pair of EDs.
20. 20 . The minimum ED finder of claim 18 , wherein the iterative comparison circuit comprises: a first comparator configured to compare the first minimum ED to a third minimum ED; a first register configured to store, as the first minimum ED, a smaller value from among the first minimum ED and the third minimum ED; a second comparator configured to compare the second minimum ED to a fourth minimum ED; and a second register configured to store, as the second minimum ED, a smaller value from among the second minimum ED and the fourth minimum ED, wherein the third minimum ED and the fourth minimum ED are based on a second ED set including an ED of each of four second symbol vector candidates from among the plurality of symbol vector candidates, and the first ED set is different from the second ED set.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0043090, filed on Mar. 31, 2023, and Korean Patent Application No. 10-2023-0071856, filed on Jun. 2, 2023, in the Korean Intellectual Property Office, the disclosures of each of which being incorporated by reference herein in their entireties. BACKGROUND Methods, apparatuses, and devices consistent with the present disclosure relate to a symbol detection method in a wireless communication system and, more particularly, to methods, apparatuses, and devices for obtaining a minimum Euclidean distance (ED) for log-likelihood ratio (LLR) calculation. A next-generation wireless communication system requires not only various services and high reliability but also a high-speed data transmission speed. Accordingly, studies on a multiple-input multiple-output (MIMO) system are being actively conducted. The burden of symbol detection may increase as a modulation order and a rank increase. Demands for reducing such burden are increasing. SUMMARY It is an aspect to provide a symbol detection method and a hardware structure related thereto. It is an aspect to provide an apparatus for obtaining a minimum Euclidean distance (ED) for log-likelihood ratio (LLR) calculation, and an operating method thereof. According to an aspect of one or more embodiments, there is provided an operating method of a modem chip, the operating method comprising receiving a first Euclidean distance (ED) set including an ED of each of n first symbol vector candidates from among a plurality of symbol vector candidates for a transmission symbol, wherein n is a natural number of 2 or greater; comparing magnitudes of the EDs of the first ED set; calculating each of a first minimum ED corresponding to a bit value of a first bit being 1 and a second minimum ED corresponding to the bit value of the first bit being 0, the first bit being from among a plurality of bits of a plurality of layers of the transmission symbol, based on first index information including results of the comparing the magnitudes of the EDs of the first ED set; updating the first minimum ED and the second minimum ED with a smallest first minimum ED and a smallest second minimum ED, respectively; and detecting the transmission symbol based on the updated first minimum ED and the updated second minimum ED. According to another aspect of one or more embodiments, there is provided a modem chip comprising a common comparator configured to receive a first Euclidean distance (ED) set including an ED of each of n first symbol vector candidates from among a plurality of symbol vector candidates for a transmission symbol, wherein n is a natural number of 2 or greater, compare magnitudes of the EDs of the first ED set, and output first index information including results of comparing the magnitudes of the EDs of the first ED set; and an index-based ED finder configured to calculate each of a first minimum ED corresponding to a bit value of a first bit being 1 and a second minimum ED of the bit value of the first bit being 0, the first bit being from among a plurality of bits of a plurality of layers of the transmission symbol, based on the first index information, and update the first minimum ED and the second minimum ED with a smallest first minimum ED and a smallest second minimum ED, respectively. According to another aspect of one or more embodiments, there is provided a minimum Euclidean distance (ED) finder comprising a common comparator configured to receive a first ED set including an ED of each of four first symbol vector candidates from among a plurality of symbol vector candidates for a transmission symbol, compare magnitudes of the EDs of the first ED set, and output first index information and second index information, the first index information comprising a first magnitude comparison result of a first pair of EDs in the first ED set and a second magnitude comparison result of a second pair of EDs in the first ED set, and the second index information comprising magnitude comparison results of remaining pairs of EDs included in the first ED set; a first classifier configured to receive the first index information and bit values of the first pair of EDs for a first bit that is one of a plurality of bits of a plurality of layers of the transmission symbol, and output a first index related to the bit values of the first bit being 1 and a second index related to the bit values of the first bit being 0; a second classifier configured to receive the first index information and bit values of the second pair of EDs for the first bit, and output a third index related to the bit values of the second pair of EDs for the first bit being 1 and a fourth index related to the bit values of the second pair of EDs for the first bit being 0; a first index-based comparator configured to receive the second index information, the first index, and the th