US-12627540-B2 - Connecting circuit and communication interface

Abstract

An embodiment is a connecting circuit connected to the preceding stage of a transmission circuit and configured to receive a data signal includes an initial voltage value holding circuit, and a terminating load connected in series with the initial voltage value holding circuit. The initial voltage value holding circuit outputs, to the terminating load, an initial voltage value obtained when no data signal is input, and sets both ends of the terminating load at the same potential by a DC component.

Inventors

• Tadashi Minotani
• Toshiki KISHI
• Masatoshi Tobayashi
• Yoshikazu Urabe

Assignees

• NTT, INC.
• NTT INNOVATIVE DEVICES CORPORATION

Dates

Publication Date

20260512

Application Date

20220325

Priority Date

20210325

Claims (16)

1. 1 . A connecting circuit connected to a preceding stage of a transmission circuit to which a data signal is input, the connecting circuit comprising: an initial voltage value holding circuit; and a terminating load connected in series with the initial voltage value holding circuit, wherein the initial voltage value holding circuit is configured to output, to the terminating load, an initial voltage value obtained when the data signal is not input, and sets both ends of the terminating load at the same potential in terms of a DC component.
2. 2 . The connecting circuit according to claim 1 , wherein the initial voltage value holding circuit includes: a frame detection circuit configured to detect an input of the data signal and output a frame detection signal; a signal delay circuit configured to delay the data signal; a sample-and-hold circuit configured to receive the data signal delayed by the signal delay circuit, detect the initial voltage value obtained when the data signal is not input, hold the initial voltage value in response to the input of the frame detection signal, and output the initial voltage value; and a voltage maintenance circuit configured to output the initial voltage value from the sample-and-hold circuit to the terminating load.
3. 3 . The connecting circuit according to claim 1 , wherein the terminating load includes a plurality of terminating loads.
4. 4 . The connecting circuit according to claim 1 , wherein the signal delay circuit is connected in parallel with the frame detection circuit.
5. 5 . The connecting circuit according to claim 1 , wherein the transmission circuit includes a plurality of transmission circuits to which a plurality of data signals are input, the termination load is provided for each of the plurality of transmission circuits, the initial voltage value holding circuit includes an inter-channel interpolation bias detection circuit configured to detect, as the initial voltage value, a signal of a low voltage among the plurality of input data signals, and a voltage maintenance circuit configured to receive an output of the inter-channel interpolation bias detection circuit and apply the output to the terminating load.
6. 6 . The connecting circuit according to claim 5 , wherein the inter-channel interpolation bias detection circuit includes a plurality of diode circuits, and a voltage source connected to an input of the voltage maintenance circuit via a resistor, wherein each of the plurality of data signals is input to one end of each of the plurality of diode circuits, and wherein the other end of each of the plurality of diode circuits is connected to the input of the voltage maintenance circuit.
7. 7 . The connecting circuit according to claim 6 , wherein when the signal of the low voltage is input to one diode circuit among the plurality of diode circuits, the inter-channel interpolation bias detection circuit is configured to output the signal of the low voltage to the voltage maintenance circuit.
8. 8 . A communication interface comprising the connecting circuit according to claim 1 .
9. 9 . The connecting circuit according to claim 2 , wherein the terminating load includes a plurality of terminating loads.
10. 10 . The connecting circuit according to claim 4 , wherein the terminating load includes a plurality of terminating loads.
11. 11 . A communication interface comprising the connecting circuit according to claim 2 .
12. 12 . A communication interface comprising the connecting circuit according to claim 3 .
13. 13 . A communication interface comprising the connecting circuit according to claim 4 .
14. 14 . A communication interface comprising the connecting circuit according to claim 5 .
15. 15 . A communication interface comprising the connecting circuit according to claim 6 .
16. 16 . A communication interface comprising the connecting circuit according to claim 7 .

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This patent application is a national phase entry of PCT application Ser. No., PCT/JP2022/014485 filed on Mar. 25, 2022, which claims priority to Japanese Patent application Ser. No., 2021-051313 filed on Mar. 25, 2021. Both of the aforementioned applications are hereby incorporated by reference in their entireties. TECHNICAL FIELD The present invention relates to a connecting circuit connected to a transmission circuit, and a communication interface. BACKGROUND To improve the data processing capability of a computer, a large amount of data needs to be transmitted/received to/from the computer. To do so, it is promising to use many high-speed interfaces such as optical communication for transmission/reception. In some cases, the chip of a CPU or GPU serving as the data processing part of the computer and the chip of an optical communication interface are separately manufactured and connected by wiring on a board. At this time, a chip capacitor for a DC block is sometimes inserted to block a DC current flowing through a path between the chip of the CPU or GPU serving as a data source and the chip of the optical communication interface. In a connection form in a conventional transmission interface 4, as shown in FIG. 8, a transmission circuit 44 is biased at a bias voltage suited to the transmission circuit 44, and a data source 3 and the communication interface 4 are separated by a chip capacitor 41 to prevent a DC current from flowing through a connection with the data source 3 to change the bias voltage. As the chip capacitor 41, a large capacitor of 0.1 μF or the like is often used. The data source 3 and the transmission circuit 44 are often connected using a transmission line 2 for transmitting a high-frequency signal with a low distortion, and a terminating load (resistor) 40 of the transmission line 2 is arranged in the transmission interface 4. In general, the terminating load 40 has a resistance of 50Ω, and the chip capacitor 41 and the terminating load 40 form a high-pass filter having a cutoff frequency of about 32 kHz. A 0.1-μF capacitor is necessary to form a high-pass filter of a cutoff frequency by arranging the chip capacitor 41 on the preceding stage of the terminating load 40 of the transmission line 2. In this connection form, the chip of the CPU or GPU serving as the data processing part of the computer is often mounted on a package substrate such as a buildup substrate. When the chip for optical communication is also mounted on the package substrate, the chip capacitor for the DC block needs to be removed because of a limited area of the package substrate. A connection form using a transmission interface 5 shown in FIG. 9 is considered, in which the chip capacitor is removed from the connection form in the conventional transmission interface 4. In this connection form, a capacitor 51 is arranged on the subsequent stage of a terminating load 50 to prevent an increase in cost caused by the formation of a 0.1-μF capacitor within the chip, and a resistor 52 having a high resistance value is arranged between a transmission circuit 54 and a bias circuit 53, forming a high-pass filter. RELATED ART LITERATURE Non-Patent Literature Non-Patent Literature 1: https://pc.watchimpress.co.jp/docs/column/kaigai/1227139.html SUMMARY Problem to be Solved by Embodiments of the Invention However, in this connection form, the terminating load 50 and the data source 3 are series-connected, and thus a DC current flows through the transmission line 2 and the terminating load 50. The DC current causes problems such as an increase in power consumption of the data source 3 and disconnection of the transmission line 2. It is an object of the present invention to provide a connecting circuit and a communication interface that can suppress a DC current flowing from a data source to a terminating load on the preceding stage of a transmission circuit without arranging a chip capacitor between the data source and a transmission interface. Means of Solution to the Problem To solve the above-described problems, according to embodiments of the present invention, there is provided a connecting circuit connected to a preceding stage of a transmission circuit to which a data signal is input, comprising an initial voltage value holding unit, and a terminating load connected in series with the initial voltage value holding unit, wherein the initial voltage value holding unit outputs, to the terminating load, an initial voltage value obtained when the data signal is not input, and sets both ends of the terminating load at the same potential by a DC component. According to embodiments of the present invention, there is provided a connecting circuit comprising a frame detection circuit, a signal delay circuit connected in parallel with the frame detection circuit, a sample-and-hold circuit configured to receive an output of the signal delay circuit, the sample-and-hold circuit receiving an ou