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US-12627553-B2 - System and design method of an ethernet controller of a combined centralized and distributed unit

US12627553B2US 12627553 B2US12627553 B2US 12627553B2US-12627553-B2

Abstract

The present invention provides an efficient hardware architecture of an Ethernet controller to provide for connectivity interfaces to a combined centralized unit and a distributed unit (CCDU) for processing Level 1, 2 and 3 scheduling in a network. The CCDU design may provide the functionality of a CU and a DU as a single unit and the design of the Ethernet controller along with an eASIC comprising an accelerator unit is very important. A single board approach of the CCDU make the CCDU more reliable and less costly.

Inventors

  • Narender Kumar
  • Shakti Singh
  • Amrish BANSAL
  • Brijesh Shah
  • Bajinder Pal SINGH
  • Selvakumar Ganesan

Assignees

  • Jio Platforms Limited

Dates

Publication Date
20260512
Application Date
20230324
Priority Date
20220331

Claims (12)

  1. 1 . A network enabled controller system for a combined centralized and distributed unit (CCDU) system, said system comprising: a housing for a controller, said controller operatively coupled to a processing unit of the CCDU, wherein the controller further comprises: an accelerator unit, said accelerator unit accelerates a set of functionalities of the CCDU; a fronthaul Network interface controller (NIC) ( 120 ), said fronthaul NIC is communicatively coupled with a radio unit (RU) ( 108 ); and a backhaul NIC communicatively coupled to a backhaul network ( 112 ); and and one or more network interfaces, wherein said controller including the accelerator unit, the fronthaul NIC, and the backhaul NIC is embedded in a single printed circuit board with the processing unit of the CCDU as a system on chip (SoC).
  2. 2 . The system as claimed in claim 1 , wherein the Fronthaul NIC ( 120 ) is configured with an interface underevolved Common Public Radio Interface (eCPRI) protocol with the Radio unit ( 108 ).
  3. 3 . The system as claimed in claim 2 , wherein the Fronthaul NIC further comprises an built-in synchronization block to perform any or a combination of enhanced Common Public Radio Interface (eCPRI) and ORAN functionality.
  4. 4 . The system as claimed in claim 1 , wherein the Backhaul NIC ( 114 ) provides connectivity with configured optical Ethernet.
  5. 5 . The system as claimed in claim 4 , wherein the backhaul NIC ( 114 ) further comprises a synchronization block to recover a Clock signal from the backhaul network ( 112 ).
  6. 6 . The system as claimed in claim 1 , wherein the accelerator unit further comprises a Soft-Decision Forward Error Correction (SD-FEC) module ( 116 ).
  7. 7 . The system as claimed in claim 6 , wherein the SD-FEC module ( 116 ) supports a Low Density Parity Check (LDPC) decoding and encoding and Turbo code decoding.
  8. 8 . The system as claimed in claim 1 , wherein at least eight dynamic random-access memory integrated circuits or modules are embedded in the single integrated board, wherein and at least five 1 GB DDR4 are connected with the single integrated circuit.
  9. 9 . The system as claimed in claim 1 , wherein the one or more connection interfaces are connected with the processing unit ( 118 ) through the platform controller Hub (PCH) ( 320 ) associated with the single integrated board.
  10. 10 . The system as claimed in claim 1 , wherein the controller is enabled by a local area network.
  11. 11 . A method performed by a network enabled controller system for a combined centralized and distributed unit (CCDU) system, the method comprising: performing a combination of enhanced Common Public Radio Interface (eCPRI) and ORAN functionality; providing connectivity by a Backhaul NIC ( 114 ) with configured optical Ethernet; recovering, by a synchronization block equipped inside the Backhaul NIC ( 114 ), a Clock signal from the backhaul network ( 112 ); and supporting, by a Soft-Decision Forward Error Correction (SD-FEC) module ( 116 ), a Low Density Parity Check (LDPC) decoding and encoding and Turbo code decoding, wherein the SD-FEC module ( 116 ) is equipped inside an accelerator unit to give a confidence factor for deciding a signal between 1 and 0.
  12. 12 . A non-transitory computer readable medium comprising processor executable instructions that cause a processor to: perform a combination of enhanced Common Public Radio Interface (eCPRI) and ORAN functionality; provide connectivity by a Backhaul NIC ( 114 ) with configured optical Ethernet; recover, by a synchronization block equipped inside the Backhaul NIC ( 114 ), a Clock signal from the backhaul network ( 112 ); and support, by a Soft-Decision Forward Error Correction (SD-FEC) module ( 116 ), a Low Density Parity Check (LDPC) decoding and encoding and Turbo code decoding, wherein the SD-FEC module ( 116 ) is equipped inside an accelerator unit to give a confidence factor for deciding a signal between 1 and 0.

Description

FIELD OF INVENTION The embodiments of the present disclosure generally relate to telecommunication basement application. More particularly, the present disclosure relates to design of an ethernet controller of a combined centralized and distributed unit (CCDU). BACKGROUND OF THE INVENTION The following description of related art is intended to provide background information pertaining to the field of the disclosure. This section may include certain aspects of the art that may be related to various features of the present disclosure. However, it should be appreciated that this section be used only to enhance the understanding of the reader with respect to the present disclosure, and not as admissions of prior art. The fifth generation (5G) technology is expected to fundamentally transform the role that telecommunications technology plays in the industry and society at large. A gNodeB is a 3GPP-compliant implementation of a 5G-NR base station. It consists of independent Network Functions, which implement 3GPP-compliant NR Radio access network (RAN) protocols namely: physical layer (PHY), media access control layer (MAC), radio link control (RLC), Packet Data Convergence Protocol (PDCP), service data adaptation protocol (SDAP), radio resource control (RRC), Network Real-time Analysis Platform (NRAP) as shown in FIG. 1A. The gNB further incorporates three functional modules: the CU, the DU and the Radio Unit (RU), which can be deployed in multiple combinations. The CU and DU can run together or independently and can be deployed on either physical (e.g. a chipset) or virtual resources (e.g. dedicated COTS server or shared cloud resources). The CU provides support for the higher layers of the protocol stack such as SDAP, PDCP and RRC while the DU provides support for the lower layers of the protocol stack such as radio link control (RLC), media access control (MAC) and Physical layer. In a 5G radio access network (RAN) architecture, the DU in the baseband unit (BBU) is responsible for real time Layer 1 and Layer 2 scheduling functions of the 5G protocol stack layer and the CU is responsible for non-real time, higher L2 and L3 of the 5G protocol stack layer. However, in existing architecture the DU and the CU units are physically separate and require exhaustive and complex methodologies and protocol support for the splitting of the gNB into the DU and CU. Splitting of CU and DU is the most outstanding in the gNB internal structure and these two entities are connected by a new interface called F1. In most existing gNB nodes, CU and DU are physically separate, that is, the CU and DU are on separate boards and hence the splitting becomes more expensive in terms of realization of temperature requirement, vibration, dust, humidity, latency, power, radiation loss, bandwidth, more dependence on possible interfaces and maintaining the parameters for both the CU and DU separately. Normally, to make the server, the provider's uses network interface card such as PCIe card, which requires separate plugins, input sources, and other external connections. Furthermore, the present available technology cannot fulfil the requirement of high speed processing, on a single integrated chip, and is complex in nature. Hence, there is a need in the art to provide for local area network controller that is embedded in a single integrated board and furthermore a compact CCDU that can overcome the shortcomings of the existing prior art. OBJECTS OF THE PRESENT DISCLOSURE Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below. An object of the present disclosure is to provide a system in a single unit to reduce cost and increase reliability. An object of the present disclosure is to design a local area network controller Hardware that is on a single PCB approach by keeping all required SoC on board. An object of the present disclosure is to provide a system that can manage one or more network interfaces in the single PCB. An object of the present disclosure is to provide a system that operates at standard telecom power supply (−48 VDC) with all required protection for telecom sites. Yet another object of the present invention is to provide high processing speed controller on an integrated chip. SUMMARY This section is provided to introduce certain objects and aspects of the present invention in a simplified form that are further described below in the detailed description. This summary is not intended to identify the key features or the scope of the claimed subject matter. In order to achieve the aforementioned objectives, the present invention provides a controller system for a combined centralized and distributed unit (CCDU) system. The system may include a housing for the controller, the controller operatively coupled to a processing unit of the CCDU. The controller may be embedded in a single integrated board. The controller further may include an accelerator unit that may sp