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US-12627617-B2 - Global system interconnect for an integrated circuit

US12627617B2US 12627617 B2US12627617 B2US 12627617B2US-12627617-B2

Abstract

Embodiments herein describe an integrated circuit (IC) which includes a global ring that interconnects multiple local rings distributed throughout the IC. In one embodiment, the global ring is connected to the local rings using respective switches. The global ring (and the switches) interconnect the local rings so that a node coupled to one of the local rings can communicate with a node connected to another local ring.

Inventors

  • Ahmad R. Ansari
  • John O'Dwyer

Assignees

  • XILINX, INC.

Dates

Publication Date
20260512
Application Date
20221228

Claims (11)

  1. 1 . An integrated circuit (IC), comprising: a global ring comprising a plurality of switches; a plurality of local rings distributed throughout the IC, wherein each of the plurality of local rings is coupled to the global ring by a respective one of the plurality of switches; and a plurality of nodes coupled to the plurality of local rings, wherein the global ring is configured to route a packet received from a first node of the plurality of nodes coupled to a first ring of the plurality of local rings to a second node of the plurality of nodes coupled to a second ring of the plurality of local rings, wherein, when receiving the packet, the second node is configured to: receive only a first portion of the packet over multiple clock cycles; determine whether the second node is the destination of the packet based on the first portion; upon determining the second node is the destination of the packet, receive a remaining portion of the packet over multiple additional clock cycles; and forward a null packet to a next node in the second ring in parallel with receiving the remaining portion of the packet during the multiple additional clock cycles.
  2. 2 . The IC of claim 1 , wherein a second packet inserted by the first node that is destined for a third node coupled to the first ring is transmitted to the third node by the first ring without traversing through the global ring.
  3. 3 . The IC of claim 2 , further comprising: a fourth node coupled to the global ring, wherein a third packet inserted by the first node that is destined for the fourth node is transmitted by the first ring and the global ring to the fourth node.
  4. 4 . The IC of claim 1 , wherein the global ring and the plurality of local rings permit packet flow in only one direction.
  5. 5 . The IC of claim 1 , wherein the packet traverses through at least two of the plurality of switches when being routed between the first and second rings by the global ring.
  6. 6 . The IC of claim 1 , wherein, before the packet is received at the second node, the packet is received at a third node coupled to the second ring, wherein the third node is configured to: receive only the first portion of the packet over multiple clock cycles; determine whether the third node is the destination of the packet based on the first portion; upon determining the third node is not the destination of the packet, receive the remaining portion of the packet over multiple additional clock cycles; and forward the first portion of the packet to the second node in parallel with receiving the remaining portion of the packet during the multiple additional clock cycles.
  7. 7 . An IC, comprising: a global ring comprising a plurality of switches; a plurality of local rings, wherein each of the plurality of local rings is coupled to the global ring by a respective one of the plurality of switches; and a plurality of nodes coupled to the plurality of local rings, wherein the global ring and at least two of the plurality of switches are used to route a packet received from a first node coupled to a first ring of the plurality of local rings to a second node coupled to a second ring of the plurality of local rings, wherein, when receiving the packet, the second node is configured to: receive only a first portion of the packet over multiple clock cycles; determine whether the second node is the destination of the packet based on the first portion; upon determining the second node is the destination of the packet, receive a remaining portion of the packet over multiple additional clock cycles; and forward a null packet to a next node in the second ring in parallel with receiving the remaining portion of the packet during the multiple additional clock cycles.
  8. 8 . The IC of claim 7 , wherein a second packet inserted by the first node that is destined for a third node coupled to the first ring is transmitted to the third node by the first ring without traversing through the global ring.
  9. 9 . The IC of claim 8 , further comprising: a fourth node coupled to the global ring, wherein a third packet inserted by the first node that is destined for the fourth node is transmitted by the first ring and the global ring to the fourth node.
  10. 10 . The IC of claim 7 , wherein at least one of the plurality of local rings includes a plurality of sub-local rings connected to the at least one local ring by a plurality of respective switches.
  11. 11 . The IC of claim 7 , wherein, before the packet is received at the second node, the packet is received at a third node coupled to the second ring, wherein the third node is configured to: receive only the first portion of the packet over multiple clock cycles; determine whether the third node is the destination of the packet based on the first portion; upon determining the third node is not the destination of the packet, receive the remaining portion of the packet over multiple additional clock cycles; and forward the first portion of the packet to the second node in parallel with receiving the remaining portion of the packet during the multiple additional clock cycles.

Description

TECHNICAL FIELD Examples of the present disclosure generally relate to ring interconnects in an integrated circuit. BACKGROUND A system on chip (SoC) (e.g., a field programmable gate array (FPGA), a programmable logic device (PLD), or an application specific integrated circuit (ASIC)) can contain a packet network structure known as a network on a chip (NoC) to route data packets between logic blocks in the SoC—e.g., programmable logic blocks, processors, memory, and the like. Because the NoC is in-band communication, typically most (or all) major communications are done through the NoC. As such, NoCs are high performance but also very costly. Additionally, many hardware blocks in a SoC do not have NoC interfaces such as transceivers, input/output (I/O) elements, voltage/temperature monitors, or phase locked loops (PLLs) since they do not require high performance. These hardware blocks may still need to communicate with each other or with a Platform Management Controller. Also, some blocks that have NoC interface still prefer to have their control be done through sideband interfaces to allow exclusivity in control and also less intrusion on their in-band traffic. SUMMARY Techniques for defining a global ring coupled to local rings in an integrated circuit are described. One example is an integrated circuit that includes a global ring comprising a plurality of switches, a plurality of local rings distributed throughout the IC wherein each of the plurality of local rings is coupled to the global ring by a respective one of the plurality of switches, and a plurality of nodes coupled to the plurality of local rings where the global ring is configured to route a packet received from a first node of the plurality of nodes coupled to a first ring of the plurality of local rings to a second node of the plurality of nodes coupled to a second ring of the plurality of local rings. Another example is a method for transmitting packets between nodes communicatively coupled by a ring in an IC. The method includes receiving only a first portion of a packet over multiple clock cycles at a first node coupled to the ring, determining whether the first node is the destination of the packet based on the first portion, upon determining the first node is the destination of the packet, receiving a remaining portion of the packet over multiple additional clock cycles at the first node, and forwarding a null packet to a next node in the ring in parallel with receiving the remaining portion of the packet during the multiple additional clock cycles. Another example is an integrated circuit that includes a global ring comprising a plurality of switches, a plurality of local rings where each of the plurality of local rings is coupled to the global ring by a respective one of the plurality of switches, a plurality of nodes coupled to the plurality of local rings where the global ring and at least two of the plurality of switches are used to route a packet received from a first node coupled to a first ring of the plurality of local rings to a second node coupled to a second ring of the plurality of local rings. BRIEF DESCRIPTION OF DRAWINGS So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope. FIG. 1 is a block diagram of a global ring interconnecting multiple local rings in an integrated circuit, according to an example. FIG. 2 illustrates transmitting packets in a ring, according to an example. FIG. 3 illustrates a switch between the global and local rings, according to an example. FIG. 4 illustrates a node connected to a ring, according to an example. FIG. 5 illustrates microarchitecture of a node connected to a ring, according to examples. FIG. 6 illustrates a controller interface, according to examples. FIG. 7 is a flowchart for transmitting packets on a ring, according to an example. To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one example may be beneficially incorporated in other examples. DETAILED DESCRIPTION Various features are described hereinafter with reference to the figures. It should be noted that the figures may or may not be drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the features. They are not intended as an exhaustive description of the description or as a limitation on the scope of the claims. In addition, an illustrated example need not have al