US-12627908-B2 - Electronic device, electronic system including the same and operating method of the electronic system

Abstract

Disclosed is an electronic device including a counter suitable for counting a clock signal and generating a count signal corresponding to a count value of the clock signal, a target count generator suitable for generating a target count signal based on the count signal and a second adjusting signal, a comparator suitable for comparing the target count signal with a reference count signal and generating a comparison signal which corresponds to a difference value between the count value corresponding to the target count signal and a count value corresponding to the reference count signal, and a count value adjuster suitable for generating the second adjusting signal corresponding to the difference value, based on the comparison signal.

Inventors

• Daisuke Shiraishi

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260512

Application Date

20230707

Priority Date

20230216

Claims (19)

1. 1 . An electronic device comprising: a counter suitable for counting a clock signal and generating a count signal corresponding to a count value of the clock signal; a target count generator suitable for generating a target count signal based on the count signal and a second adjusting signal; a comparator suitable for comparing the target count signal with a reference count signal and generating a comparison signal which corresponds to a difference value between the count value corresponding to the target count signal and a count value corresponding to the reference count signal; and a count value adjuster suitable for generating the second adjusting signal corresponding to the difference value, based on the comparison signal.
2. 2 . The electronic device of claim 1 , further comprising: a line value adjuster suitable for generating a first adjusting signal corresponding to the difference value, based on the comparison signal; and a clock generator suitable for generating the clock signal for each predetermined period and adjusting a toggling number of the clock signal, based on the first adjusting signal.
3. 3 . The electronic device of claim 1 , further comprising an interface suitable for receiving the reference count signal from an external device.
4. 4 . The electronic device of claim 1 , further comprising: a row-controller suitable for generating row-control signals for each predetermined period, based on the clock signal; a pixel array suitable for generating pixel signals for each predetermined period, based on the row-control signals; and a signal converter suitable for converting the pixel signals into digital signals.
5. 5 . An electronic system comprising: a first electronic device suitable for obtaining first image frames for each frame period, based on a first clock signal and generating a first count signal corresponding to the first clock signal; and a second electronic device suitable for obtaining second image frames for each frame period, based on a second clock signal, and adjusting a toggling number of the second clock signal for each frame period, based on the first count signal and the second clock signal, wherein the first electronic device includes: a first clock generator suitable for generating the first clock signal having a predetermined toggling number for each frame period, based on a first adjusting signal; a first row-controller suitable for generating first row-control signals for each frame period, based on the first clock signal; a first pixel array suitable for generating first pixel signals for each frame period, based on the first row-control signals; a first signal converter suitable for converting the first pixel signals into first digital signals; and a first synchronization controller suitable for generating the first adjusting signal and the first count signal, based on the first clock signal, a first identification signal and a first setting signal.
6. 6 . The electronic system of claim 5 , wherein a cycle of the first clock signal is equal to a cycle of the second clock signal.
7. 7 . The electronic system of claim 5 , wherein the first electronic device includes: a first image sensor including the first clock generator, the first row-controller, the first pixel array, the first signal converter, and the first synchronization controller suitable for obtaining the first image frames, based on the first clock signal, and counting a toggling number of the first clock signal to generate a first toggling count signal; and a first interface suitable for receiving the first toggling count signal and outputting the first count signal.
8. 8 . The electronic system of claim 5 , wherein the first synchronization controller includes: a first counter suitable for counting the first clock signal and generating the first count signal corresponding to a first count value of the first clock signal; a first target count generator disabled according to the first identification signal; a first comparator disabled according to the first identification signal; a first count value adjuster disabled according to the first identification signal; and a first line value adjuster suitable for generating the first adjusting signal corresponding to a first default value, based on the first identification signal and the first setting signal.
9. 9 . The electronic system of claim 7 , wherein the first interface includes: a first transmitter enabled according to a first identification signal and suitable for transmitting the first count signal to the second image sensor; and a receiver disabled according to the first identification signal.
10. 10 . The electronic system of claim 5 , wherein the second electronic device includes: a second image sensor suitable for obtaining the second image frames, based on the second clock signal, and adjusting the toggling number of the second clock signal, based on a first reference count signal and the second clock signal; and a second interface suitable for receiving the first count signal and outputting the first reference count signal.
11. 11 . The electronic system of claim 10 , wherein the second image sensor includes: a second clock generator suitable for generating the second clock signal for each frame period and adjusting the toggling number of the second clock signal, based on a third adjusting signal; a second row-controller suitable for generating second row-control signals for each frame period, based on the second clock signal; a second pixel array suitable for generating second pixel signals for each frame period, based on the second row-control signals; a second signal converter suitable for converting the second pixel signals into second digital signals; and a second synchronization controller suitable for generating the third adjusting signal and a second count signal, based on the first count signal, the second clock signal, a second identification signal and a second setting signal.
12. 12 . The electronic system of claim 11 , wherein the second synchronization controller includes: a second counter suitable for counting the second clock signal and generating the second count signal corresponding to a second count value of the second clock signal; a second target count generator enabled according to the second identification signal and suitable for generating a second target count signal, based on the second count signal and a fourth adjusting signal; a second comparator enabled according to the second identification signal and suitable for comparing the second target count signal with the first count signal and generating a comparison signal corresponding to a difference value between the second count value corresponding to the second target count signal and a first count value corresponding to the first count signal; a second count value adjuster enabled according to the second identification signal and suitable for generating the fourth adjusting signal corresponding to the difference value, based on the comparison signal; and a second line value adjuster suitable for generating the third adjusting signal corresponding to the difference value, based on the second identification signal, the second setting signal and the comparison signal.
13. 13 . The electronic system of claim 10 , wherein the second interface includes: a second transmitter disabled according to a second identification signal; and a second receiver enabled according to the second identification signal and suitable for receiving the first count signal from the first image sensor.
14. 14 . The electronic system of claim 5 , wherein the first count signal is transmitted from the first electronic device to the second electronic device through a wireless communication network.
15. 15 . The electronic system of claim 14 , wherein the wireless communication network includes a Wi-Fi network.
16. 16 . An operating method of an electronic system, comprising: providing, by a first electronic device, a second electronic device with a first count signal generated by a first image sensor; comparing, by the second electronic device, the first count signal with a second count signal generated by a second image sensor; and adjusting, by the second image sensor, a second frame period of the second image sensor while maintaining, by the first image sensor, a first frame period when, as a result of the comparing, a first count value corresponding to the first count signal is different from a second count value corresponding to the second count signal.
17. 17 . The operating method of claim 16 , wherein the adjusting is performed until the first count signal becomes equal to the second count signal.
18. 18 . The operating method of claim 17 , wherein the adjusting includes returning the second frame period to its original frame period when the first count signal becomes equal to the second count signal.
19. 19 . The operating method of claim 16 , wherein: the second frame period includes an active period and a blank period, the active period includes a plurality of row-line periods corresponding to a plurality of rows of a second pixel array included in the second image sensor, the blank period is between a current active period and a next active period, and the adjusting includes adjusting the blank period.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0020743, filed on Feb. 16, 2023, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND 1. Field Various embodiments of the present disclosure relate to a semiconductor design technique, and more particularly, to an electronic device including an image sensor, an electronic system including the electronic device, and an operating method of the electronic system. 2. Description of the Related Art Image sensors are devices for capturing images using the property of a semiconductor which reacts to light. Image sensors may be roughly classified into charge-coupled device (CCD) image sensors and complementary metal-oxide semiconductor (CMOS) image sensors. Recently, CMOS image sensors are widely used because the CMOS image sensors can allow both analog and digital control circuits to be directly implemented on a single integrated circuit (IC). SUMMARY Various embodiments of the present disclosure are directed to an electronic device capable of synchronizing image frames when recording a video, an electronic system including the electronic device, and an operating method of the electronic system. In accordance with an embodiment of the present disclosure, an electronic device may include: a counter suitable for counting a clock signal and generating a count signal corresponding to a count value of the clock signal; a target count generator suitable for generating a target count signal based on the count signal and a second adjusting signal; a comparator suitable for comparing the target count signal with a reference count signal and generating a comparison signal which corresponds to a difference value between the count value corresponding to the target count signal and a count value corresponding to the reference count signal; and a count value adjuster suitable for generating the second adjusting signal corresponding to the difference value, based on the comparison signal. In accordance with an embodiment of the present disclosure, an electronic system may include: a first electronic device suitable for obtaining first image frames for each frame period, based on a first clock signal and generating a first count signal corresponding to the first clock signal; and a second electronic device suitable for obtaining second image frames for each frame period, based on a second clock signal, and adjusting a toggling number of the second clock signal for each frame period, based on the first count signal and the second clock signal. In accordance with an embodiment of the present disclosure, an operating method of an electronic system may include: providing, by a first electronic device, a second electronic device with a first count signal generated by a first image sensor; comparing, by the second electronic device, the first count signal with a second count signal generated by a second image sensor; and adjusting, by the second image sensor, a second frame period of the second image sensor while maintaining, by the first image sensor, a first frame period when, as a result of the comparing, a first count value corresponding to the first count signal is different from a second count value corresponding to the second count signal. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating an electronic system in accordance with an embodiment of the present disclosure. FIG. 2 is a block diagram illustrating a first image sensor illustrated in FIG. 1. FIG. 3 is a block diagram illustrating a pixel array illustrated in FIG. 2. FIG. 4 is a block diagram illustrating a synchronization controller illustrated in FIG. 2. FIG. 5 is a block diagram illustrating a first interface illustrated in FIG. 1. FIG. 6 is a block diagram illustrating a second image sensor illustrated in FIG. 1. FIG. 7 is a block diagram illustrating a pixel array illustrated in FIG. 6. FIG. 8 is a block diagram illustrating a synchronization controller illustrated in FIG. 6. FIGS. 9 to 12 are diagrams additionally illustrating an operation of a comparator illustrated in FIG. 8 in accordance with an embodiment of the present disclosure. FIG. 13 is a block diagram illustrating a second interface illustrated in FIG. 1. FIG. 14 is a diagram illustrating an operation of the electronic system illustrated in FIG. 1. FIG. 15 is a diagram additionally illustrating an operation of the electronic system illustrated in FIG. 10 in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION Various embodiments of the present disclosure are described below with reference to the accompanying drawings, in order to describe in detail the present disclosure so that those with ordinary skill in art to which the present disclosure pertains may easily carry out the technical spirit of the present disclosure. It will be understood that when an element is referred to as being “co