US-12628271-B2 - Electronic component

US12628271B2US 12628271 B2US12628271 B2US 12628271B2US-12628271-B2

Abstract

To prevent interfacial peeling due to the stress of an insulating layer in a capacitor-inductor integrated electronic component having three or more conductor layers. An electronic component includes: a conductor layer M 1 including a conductor pattern constituting an inductor; a conductor pattern overlapping a part of the conductor pattern through a dielectric film; an insulating layer covering the conductor layer M 1 and conductor pattern; a conductor layer M 2 provided on the insulating layer and including a conductor pattern constituting the inductor; and an insulating layer covering the conductor layer M 2 . The conductor layer M 2 is formed to be branching from or independently of the conductor pattern and further includes a dummy pattern overlapping the conductor pattern. This prevents the stress of the insulating layer from being directly applied to the conductor pattern to thereby prevent peeling at the interface between the conductor layer M 1 and the dielectric film.

Inventors

Yu FUKAE
Tomoya HANAI
Yusuke OBA
Kenichi Yoshida
Katsuharu Yasuda
Takashi Ohtsuka

Assignees

TDK CORPORATION

Dates

Publication Date: 20260512
Application Date: 20210913
Priority Date: 20200928

Claims (11)

1 . An electronic component comprising: a first conductor layer including a first inductor pattern; an upper electrode of a capacitor overlapping a part of the first inductor pattern through a dielectric film; a first insulating layer covering the first conductor layer and the upper electrode; a second conductor layer being disposed on the first insulating layer and including a second inductor pattern; and a second insulating layer covering the second conductor layer, wherein one end of the second inductor pattern is connected to one end of the first inductor pattern through a first via formed in the first insulating layer, wherein the part of the first inductor pattern is configured to form a lower electrode of the capacitor, wherein the second conductor layer further includes a dummy pattern formed to be branching from, or independently of, the second inductor pattern, and wherein the dummy pattern covers the upper electrode via the first insulating layer such that a part of the first insulating layer is sandwiched between the upper electrode and the dummy pattern in a stacking direction.
2 . The electronic component as claimed in claim 1 , wherein the upper electrode is connected to the second inductor pattern through a second via formed in the first insulating layer.
3 . The electronic component as claimed in claim 2 , wherein the second via is smaller than the upper electrode.
4 . The electronic component as claimed in claim 1 , wherein the second conductor layer further includes a conductor pattern, wherein the conductor pattern is separated from the second inductor pattern in a surface of the second conductor layer, and is connected to the upper electrode through a second via formed in the first insulating layer.
5 . The electronic component as claimed in claim 1 , wherein the dummy pattern is formed to be branching from the second inductor pattern, and the upper electrode is entirely covered with the dummy pattern or second inductor pattern.
6 . The electronic component as claimed in claim 1 , wherein the upper electrode has a lower surface facing the lower electrode with the dielectric film interposed therebetween and an upper surface facing the dummy pattern with the first insulating layer interposed therebetween.
7 . The electronic component as claimed in claim 1 , wherein the upper electrode includes a seed layer and a plating layer provided on the seed layer.
8 . The electronic component as claimed in claim 1 , wherein the first inductor pattern includes a first section extending in a first direction and a second section extending in a second direction different from the first direction, and wherein the upper electrode includes a third section extending in the first direction so as to overlap the first section of the first inductor pattern and a fourth section extending in the second direction so as to overlap the second section of the first inductor pattern.
9 . The electronic component as claimed in claim 8 , wherein the second inductor pattern extends in the first direction so as to overlap the first section of the first inductor pattern and the third section of the upper electrode, and wherein the dummy pattern extends in the second direction so as to overlap the second section of the first inductor pattern and the fourth section of the upper electrode.
10 . An electronic component comprising: a first conductor layer including a first inductor pattern; an upper electrode of a capacitor overlapping a part of the first inductor pattern through a dielectric film; a first insulating layer covering the first conductor layer and the upper electrode; a second conductor layer being disposed on the first insulating layer and including a second inductor pattern; and a second insulating layer covering the second conductor layer, wherein one end of the second inductor pattern is connected to one end of the first inductor pattern through a first via formed in the first insulating layer, the part of the first inductor pattern is configured to form a lower electrode of the capacitor, the second conductor layer includes a dummy pattern, the dummy pattern covering the upper electrode and being formed to be branching from, or independently of, the second inductor pattern, wherein the dummy pattern is formed to be independent of the second inductor pattern, and the upper electrode is entirely covered with the dummy pattern or second inductor pattern except a part that overlaps a slit separating the dummy pattern and the second inductor pattern.
11 . An electronic component comprising: a first conductor layer including a first inductor pattern; an upper electrode of a capacitor overlapping a part of the first inductor pattern through a dielectric film; a first insulating layer covering the first conductor layer and the upper electrode; a second conductor layer being disposed on the first insulating layer and including a second inductor pattern; and a second insulating layer covering the second conductor layer, wherein one end of the second inductor pattern is connected to one end of the first inductor pattern through a first via formed in the first insulating layer, the part of the first inductor pattern is configured to form a lower electrode of the capacitor, the second conductor layer includes a dummy pattern, the dummy pattern covering the upper electrode and being formed to be branching from, or independently of, the second inductor pattern, and wherein the dummy pattern includes a plurality of openings exposing the first insulating layer.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is the U.S. National Phase under 35 U.S.C. § 371 of International Application No. PCT/JP2021/033550, filed on Sep. 13, 2021, which claims the benefit of Japanese Application No. 2020-162536, filed on Sep. 28, 2020, the entire contents of each are hereby incorporated by reference. TECHNICAL FIELD The present disclosure relates to an electronic component and, more particularly, to an electronic component integrating a capacitor and an inductor. Background Art As an electronic component integrating a capacitor and an inductor, an electronic component described in Patent Document 1 is known. The electronic component described in Patent Document 1 uses two conductor layers to constitute a series circuit of the capacitor and inductor. CITATION LIST Patent Document [Patent Document 1] JP 2008-034626A SUMMARY OF THE INVENTION Problem to be Solved by the Invention However, using three or more conductor layers for achieving an electronic component with higher function involves an increase in the stress of an insulating layer for insulating the conductor layers from one another, which may cause peeling at the interface between the stacked layers due to the stress of the insulating layer. It is therefore an object of the present disclosure to prevent interfacial peeling due to the stress of the insulating layer in a capacitor-inductor integrated electronic component having three or more conductor layers. Means for Solving the Problem An electronic component according to the present disclosure includes: a first conductor layer including a first inductor pattern; a capacitor upper electrode overlapping a part of the first inductor pattern through a dielectric film; a first insulating layer covering the first conductor layer and upper electrode; a second conductor layer provided on the first insulating layer and including a second inductor pattern; and a second insulating layer covering the second conductor layer. One end of the second inductor pattern is connected to one end of the first inductor pattern through a first via formed in the first insulating layer. The part of the first inductor pattern functions as a capacitor lower electrode. The second conductor layer includes a dummy pattern overlapping the upper electrode and provided branching from or independently of the second inductor pattern. According to the present disclosure, the presence of the dummy pattern overlapping the upper electrode prevents the stress of the second insulating layer from being directly applied to the upper electrode. This reduces the stress to be applied to the upper electrode to thereby prevent peeling at the interface between the first conductor layer and the dielectric film immediately below the upper electrode. In the present disclosure, the upper electrode may be connected to the second inductor pattern through a second via formed in the first insulating layer. This can constitute a parallel circuit of a capacitor and an inductor. Alternatively, the second conductor layer may further include a conductor pattern provided separated from the second inductor pattern in the surface thereof, and the upper electrode may be connected to the conductor pattern through the second via formed in the first insulating layer. That is, the capacitor upper electrode and second inductor pattern need not be directly connected to each other. In the present disclosure, the dummy pattern may be provided branching from the second inductor pattern, and the upper electrode may be entirely covered with or entirely overlapped by the dummy pattern or second inductor pattern. This can further reduce a stress to be applied to the upper electrode. In the present disclosure, the dummy pattern may be provided independently of the second inductor pattern, and the upper electrode may be entirely covered with the dummy pattern or second inductor pattern except a part thereof that overlaps a slit separating the dummy pattern and the second inductor pattern. This prevents a variation in characteristics of the second inductor pattern caused due to the presence of the dummy pattern, facilitating designing. In the present disclosure, the dummy pattern may have a plurality of openings exposing the first insulating layer. This makes it possible to release gas generated during curing of the first insulating layer from the openings even when the dummy pattern is large in area. Advantageous Effects of the Invention As described above, according to the present disclosure, it is possible to prevent interfacial peeling due to the stress of the insulating layer in a capacitor-inductor integrated electronic component having three or more conductor layers. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view for expanding the structure of an electronic component 1 according to one embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view taken along the line A-A in FIG. 1. FIG. 3 is a schemati