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US-12628274-B2 - Wiring board

US12628274B2US 12628274 B2US12628274 B2US 12628274B2US-12628274-B2

Abstract

A wiring board includes an insulation layer and an electrical conductor layer that are layered. The insulation layer is a glass ceramic. The electrical conductor layer is a sintered body of a plurality of crystallites containing copper as a main component. The plurality of crystallites include polygonal crystallites having linear sides. The plurality of crystallites are in contact with each other via the linear sides as grain boundaries.

Inventors

  • Toshifumi Higashi
  • Hiroaki Sano
  • Akira Imoto
  • Sentarou Yamamoto

Assignees

  • KYOCERA CORPORATION

Dates

Publication Date
20260512
Application Date
20220124
Priority Date
20210128

Claims (14)

  1. 1 . A wiring board comprising: an insulation layer and an electrical conductor layer that are layered, the insulation layer and the electrical conductor layer being in contact with each other, wherein the insulation layer is a glass ceramic, the electrical conductor layer is a sintered body of a plurality of crystallites containing copper as a main component, the plurality of crystallites comprises polygonal crystallites having linear sides, the crystallites being in contact with each other via the linear sides as grain boundaries, the electrical conductor layer contains silica particles, and the electrical conductor layer has a recessed portion on a surface along the insulation layer; wherein: the silica particles are present on and within 1 μm of a surface of the electrical conductor layer that faces the insulation layer, the silica particles have an average particle diameter of 10 nm or more and 80 nm or less; a width of the recessed portion in a direction along the insulation layer is 50% or more of an average thickness of the electrical conductor layer, the recessed portion has a radius of curvature of 10 μm or more and 30 μm or less, and 70% or more of a number of crystallites among the plurality of crystallites have two or more linear sides.
  2. 2 . The wiring board according to claim 1 , wherein a width of the recessed portion in a direction along the insulation layer is 70% or more of an average thickness of the electrical conductor layer.
  3. 3 . The wiring board according to claim 2 , wherein the width of the recessed portion is 90% or less of the average thickness of the electrical conductor layer.
  4. 4 . The wiring board according to claim 1 , wherein at least two surfaces of the electrical conductor layer are sandwiched by the insulation layer, and the at least two surfaces have projecting and recessed portions along the insulation layer.
  5. 5 . The wiring board according to claim 1 , wherein the electrical conductor layer contains copper as a metal component, and a content of the copper is 80 mass % or more and 99 mass % or less.
  6. 6 . The wiring board according to claim 1 , wherein the electrical conductor layer has an interface electrical conductivity of 78% or more from 30 GHz to 49 GHz, inclusive.
  7. 7 . The wiring board according to claim 1 , wherein the silica particles are present as discrete, isolated particles on the surface of the electrical conductor layer facing the insulation layer rather than as a continuous film.
  8. 8 . The wiring board according to claim 1 , wherein the silica particles have an average particle diameter of about 30 nm.
  9. 9 . The wiring board according to claim 8 , wherein a percentage of an integrated amount between 20 nm and 40 nm is 70% or more.
  10. 10 . The wiring board according to claim 1 , wherein the recessed portion has a maximum depth of 1 μm or more and 3 μm or less.
  11. 11 . The wiring board according to claim 1 , wherein a difference between a maximum thickness and a minimum thickness of the electrical conductor layer is 1 μm or more and 3 μm or less.
  12. 12 . The wiring board according to claim 2 , wherein a side of a crystallite is determined to be a linear side when a straight line is brought into contact with the side and the side coincides with the straight line over a length corresponding to at least one-half of a longest diameter (d_MAX) of the crystallite.
  13. 13 . The wiring board according to claim 1 , wherein the electrical conductor layer is obtained by sintering a copper-particle paste including the silica particles in a reducing atmosphere comprising nitrogen and hydrogen at a peak temperature of 900° C. to 1000° C.
  14. 14 . The wiring board according to claim 1 , wherein the silica particles are silicon dioxide (SiO 2 ).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is National Stage Application of International Application No. PCT/JP2022/002423, filed on Jan. 24, 2022, which designates the United States, incorporated herein by reference, and which claims the benefit of priority from Japanese Patent Application No. 2021-012421, filed on Jan. 28, 2021, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD An embodiment of the present disclosure relates to a wiring board. BACKGROUND OF INVENTION Conventionally, a known wiring board includes an insulation layer and an electrical conductor layer containing copper as a main component. Such a wiring board is obtained, for example, by simultaneously firing an electrical conductor layer in which a metal oxide is added to copper powder and a glass ceramic as an insulation layer material. CITATION LIST Patent Literature Patent Document 1: JP 2003-277852 A SUMMARY In an aspect of the present disclosure, a wiring board includes an insulation layer and an electrical conductor layer that are layered. The insulation layer is a glass ceramic. The electrical conductor layer is a sintered body of a plurality of crystallites containing copper as a main component. The plurality of crystallites include polygonal crystallites each having linear sides, and the crystallites are in contact with each other via the linear sides as grain boundaries. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view illustrating an example of a wiring board according to an embodiment. FIG. 2 is an enlarged view of a region A illustrated in FIG. 1. FIG. 3 is an explanatory diagram illustrating an evaluation method for crystallites. FIG. 4 is a diagram showing the evaluation results of a plurality of crystallites contained in an electrical conductor layer. FIG. 5 is a graph showing the relationship between the frequency and the interface electrical conductivity in the wiring boards according to a practical example and a reference example. DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a wiring board disclosed in the present disclosure will be described with reference to the accompanying drawings. The present disclosure is not limited by the following embodiment. FIG. 1 is a cross-sectional view illustrating an example of a wiring board according to an embodiment. As illustrated in FIG. 1, in the embodiment, a wiring board 1 includes an insulation layer 20 and an electrical conductor layer 10. The insulation layer 20 is a glass ceramic. The insulation layer 20 may include a first layer 21 and a second layer 22 that face each other with the electrical conductor layer 10 interposed therebetween. The first layer 21 and the second layer 22 are located to sandwich both surfaces of the electrical conductor layer 10 in the thickness direction. The electrical conductor layer 10 contains copper as a main component. Specifically, the electrical conductor layer 10 contains 50 mass % or more of copper. The electrical conductor layer 10 may contain 70 mass % or more, 80 mass % or more, or 90 mass % or more and less than 100 mass % (99 mass % or less) of copper. The electrical conductor layer 10 is a sintered body of a plurality of crystallites. FIG. 2 is an enlarged view of a region A illustrated in FIG. 1. As illustrated in FIG. 2, the electrical conductor layer 10 includes crystallites 11 having a polygonal shape in a cross-sectional view. A plurality of adjacent crystallites 11a, 11b are in contact with each other via linear sides as grain boundaries 12 of the crystallites 11. Accordingly, interface electrical conductivity at high frequencies can be enhanced. A wiring board exhibiting high interface electrical conductivity at high frequencies can be obtained. Here, an evaluation method for the “linear sides” of the crystallites 11 will be described with reference to FIG. 3. FIG. 3 is a diagram illustrating an evaluation method for crystallites. As illustrated in FIG. 3, the crystallite 11 has a polygonally shaped cross section. The crystallite 11 illustrated as an example in FIG. 3 has an octagonal contour having sides S01 to S08. For an image obtained by photographing the electrical conductor layer 10 including the cross section, for example, a scale (or ruler) 30 is prepared and positioned along the side S01. When the length of a portion of the side S01, which extends along the scale (or ruler) 30 is at least half the longest diameter dMAX of the crystallite 11, the side is defined as a “linear side”. For each of the other sides S02 to S08, whether the side is a “linear side” is evaluated in the same way as the side S01. In the example illustrated in FIG. 3, the side S01 having a length L01 and the side S07 having a length L07 are evaluated as “linear sides”. That is, the crystallite 11 illustrated in FIG. 3 has two “linear sides”. The longest diameter dMAX of the crystallite 11 is preferably 1 μm or more and 10 μm or less. For example, for the electrical conductor