Search

US-12628283-B2 - Wiring substrate

US12628283B2US 12628283 B2US12628283 B2US 12628283B2US-12628283-B2

Abstract

A wiring substrate includes a first insulating layer, a conductor layer formed on the first insulating layer and including a wiring pattern, an organic coating film formed on the conductor layer such that the organic coating film is formed on the wiring pattern of the conductor layer, and a second insulating layer formed on the first insulating layer such that the second insulating layer is covering the conductor layer. The conductor layer is formed such that the wiring pattern has a polished surface on the opposite side with respect to the first insulating layer, and the organic coating film is formed on the wiring pattern of the conductor layer such that the organic coating film is covering the polished surface of the wiring pattern.

Inventors

  • Toshiki Furutani

Assignees

  • IBIDEN CO., LTD.

Dates

Publication Date
20260512
Application Date
20230628
Priority Date
20220701

Claims (20)

  1. 1 . A wiring substrate, comprising: a first insulating layer; a conductor layer formed on the first insulating layer and including a wiring pattern; an organic coating film formed on the conductor layer such that the organic coating film is formed on the wiring pattern of the conductor layer and covering a side surface of the wiring pattern; and a second insulating layer formed on the first insulating layer such that the second insulating layer is covering the conductor layer, wherein the organic coating film is formed such that a root mean square height of the surface of the organic coating film is in a range of 0.010 μm to 0.100 μm, the conductor layer is formed such that the wiring pattern has a polished surface on an opposite side with respect to the first insulating layer and includes a first wiring and a second wiring formed adjacent to the first wiring, that each of the first wiring and the second wiring has a wiring width of 5 μm or less, and that a distance between the first wiring and the second wiring is 7 μm or less, the organic coating film is formed on the wiring pattern of the conductor layer such that the organic coating film is covering the polished surface of the wiring pattern, and the conductor layer includes a seed layer formed on the first insulating layer, and an electrolytic plating film formed on the seed layer such that the conductor layer is formed by forming a plating resist formed on the seed layer, forming on the seed layer exposed from the plating resist the electrolytic plating film having a thickness larger than a thickness of the plating resist, and reducing the thickness of the electrolytic plating film and the thickness of the plating resist by polishing.
  2. 2 . The wiring substrate according to claim 1 , wherein the conductor layer is formed such that the wiring pattern has an aspect ratio in a range of 2.0 to 4.0.
  3. 3 . The wiring substrate according to claim 2 , wherein the polished surface of the wiring pattern of the conductor layer has a surface structure formed by chemical mechanical polishing or sandblasting.
  4. 4 . The wiring substrate according to claim 3 , further comprising: a second conductor layer formed on the first insulating layer on an opposite side with respect to the conductor layer; and a via conductor comprising the electrolytic plating film filling a through hole penetrating through the first insulating layer such that the via conductor is connecting the conductor layer and the second conductor layer.
  5. 5 . The wiring substrate according to claim 4 , wherein the via conductor is formed such that the via conductor has an aspect ratio in a range of 0.5 to 1.0.
  6. 6 . The wiring substrate according to claim 2 , further comprising: a second conductor layer formed on the second insulating layer; and a via conductor formed in the second insulating layer such that the via conductor is connecting the first conductor layer and the second conductor layer, wherein the conductor layer includes a conductor pad such that the conductor pad is connected to the via conductor, and the organic coating film is formed on the conductor layer such that the organic coating film is covering a surface of the conductor pad on an opposite side with respect to the first insulating layer and a side surface of the conductor pad except for a portion connected to the via conductor.
  7. 7 . The wiring substrate according to claim 6 , wherein the via conductor is formed such that the via conductor has an aspect ratio in a range of 0.5 to 1.0.
  8. 8 . The wiring substrate according to claim 2 , wherein the conductor layer is formed such that the seed layer includes a sputtering film.
  9. 9 . The wiring substrate according to claim 1 , wherein the conductor layer is formed such that the conductor layer has a thickness in a range of 7 μm to 20 μm.
  10. 10 . The wiring substrate according to claim 9 , wherein the conductor layer is formed such that the wiring pattern has an aspect ratio in a range of 2.0 to 4.0.
  11. 11 . The wiring substrate according to claim 9 , further comprising: a second conductor layer formed on the second insulating layer; and a via conductor formed in the second insulating layer such that the via conductor is connecting the first conductor layer and the second conductor layer, wherein the conductor layer includes a conductor pad such that the conductor pad is connected to the via conductor, and the organic coating film is formed on the conductor layer such that the organic coating film is covering a surface of the conductor pad on an opposite side with respect to the first insulating layer and a side surface of the conductor pad except for a portion connected to the via conductor.
  12. 12 . The wiring substrate according to claim 11 , wherein the via conductor is formed such that the via conductor has an aspect ratio in a range of 0.5 to 1.0.
  13. 13 . The wiring substrate according to claim 1 , wherein the polished surface of the wiring pattern of the conductor layer has a surface structure formed by chemical mechanical polishing or sandblasting.
  14. 14 . The wiring substrate according to claim 13 , further comprising: a second conductor layer formed on the first insulating layer on an opposite side with respect to the conductor layer; and a via conductor comprising the electrolytic plating film filling a through hole penetrating through the first insulating layer such that the via conductor is connecting the conductor layer and the second conductor layer.
  15. 15 . The wiring substrate according to claim 14 , wherein the via conductor is formed such that the via conductor has an aspect ratio in a range of 0.5 to 1.0.
  16. 16 . The wiring substrate according to claim 13 , wherein the conductor layer is formed such that the seed layer includes a sputtering film.
  17. 17 . The wiring substrate according to claim 1 , further comprising: a second conductor layer formed on the second insulating layer; and a via conductor formed in the second insulating layer such that the via conductor is connecting the first conductor layer and the second conductor layer, wherein the conductor layer includes a conductor pad such that the conductor pad is connected to the via conductor, and the organic coating film is formed on the conductor layer such that the organic coating film is covering a surface of the conductor pad on an opposite side with respect to the first insulating layer and a side surface of the conductor pad except for a portion connected to the via conductor.
  18. 18 . The wiring substrate according to claim 17 , wherein the conductor layer is formed such that the conductor layer has a thickness in a range of 7 μm to 20 μm.
  19. 19 . The wiring substrate according to claim 17 , wherein the via conductor is formed such that the via conductor has an aspect ratio in a range of 0.5 to 1.0.
  20. 20 . The wiring substrate according to claim 1 , wherein the conductor layer is formed such that the seed layer includes a sputtering film.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2022-107239, filed Jul. 1, 2022, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a wiring substrate. Description of Background Art Japanese Patent Application Laid-Open Publication No. 2003-258410 describes a method of manufacturing a wiring substrate in which an electroless copper plating layer and an electrolytic copper plating layer are sequentially laminated on an insulating substrate to form a wiring pattern. The entire contents of this publication are incorporated herein by reference. SUMMARY OF THE INVENTION According to one aspect of the present invention, a wiring substrate includes a first insulating layer, a conductor layer formed on the first insulating layer and including a wiring pattern, an organic coating film formed on the conductor layer such that the organic coating film is formed on the wiring pattern of the conductor layer, and a second insulating layer formed on the first insulating layer such that the second insulating layer is covering the conductor layer. The conductor layer is formed such that the wiring pattern has a polished surface on the opposite side with respect to the first insulating layer, and the organic coating film is formed on the wiring pattern of the conductor layer such that the organic coating film is covering the polished surface of the wiring pattern. According to another aspect of the present invention, a method of manufacturing a wiring substrate includes forming a conductor layer on a first insulating layer such that the conductor layer has a wiring pattern, forming an organic coating film on the conductor layer such that the organic coating film is formed on the wiring pattern of the conductor layer, and forming a second insulating layer on the first insulating layer such that the second insulating layer covers the conductor layer. The forming of the conductor layer includes forming a seed layer on the first insulating layer, forming a plating resist on the seed layer, forming an electrolytic plating film having a thickness larger than a thickness of the plating resist on the seed layer exposed from the plating resist, and polishing the electrolytic plating film and the plating resist such that the thickness of the electrolytic plating film and the thickness of the plating resist are reduced and that the wiring pattern has a polished surface on the opposite side with respect to the first insulating layer, and the forming of the organic coating film includes forming the organic coating film on the wiring pattern of the conductor layer such that the organic coating film covers the polished surface of the wiring pattern. BRIEF DESCRIPTION OF THE DRAWINGS A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: FIG. 1 is a cross-sectional view illustrating an example of a wiring substrate according to an embodiment of the present invention; FIG. 2 is a partial enlarged cross-sectional view of the wiring substrate of FIG. 1; FIG. 3A is a cross-sectional view illustrating an example of a manufacturing process of a wiring substrate according to an embodiment of the present invention; FIG. 3B is a cross-sectional view illustrating an example of a manufacturing process of a wiring substrate after FIG. 3A; FIG. 3C is a cross-sectional view illustrating an example of a manufacturing process of a wiring substrate after FIG. 3B; FIG. 3D is a cross-sectional view illustrating an example of a manufacturing process of a wiring substrate after FIG. 3C; FIG. 3E is a cross-sectional view illustrating an example of a manufacturing process of a wiring substrate after FIG. 3D; FIG. 3F is a cross-sectional view illustrating an example of a manufacturing process of a wiring substrate after FIG. 3E; FIG. 3G is a partial enlarged view illustrating in detail a manufacturing process of a wiring substrate after FIG. 3F; FIG. 3H is a partial enlarged view illustrating in detail a manufacturing process of a wiring substrate after FIG. 3G; FIG. 3I is a partial enlarged view illustrating in detail a manufacturing process of a wiring substrate after FIG. 3H; FIG. 3J is a cross-sectional view illustrating an example of a manufacturing process of a wiring substrate after FIG. 3I; FIG. 3K is a cross-sectional view illustrating an example of a manufacturing process of a wiring substrate after FIG. 3J; FIG. 3L is a cross-sectional view illustrating an example of a manufacturing process of a wiring substrate after FIG. 3K; FIG. 3M is a cross-sectional view illustrating an example of a manufacturing process of a wiring substrate after FIG