US-12628327-B2 - SRAM device for FPGA application

Abstract

A device includes a first transistor including a first drain/source terminal and a second transistor including a first gate terminal. A first conductive path is electrically connected between the first drain/source terminal and the first gate terminal. The first conductive path includes a first conductive via electrically connected between the first drain/source terminal and a first track of a first conductive layer, and a second conductive via electrically connected between the first track of the first conductive layer and a first track of a second conductive layer.

Inventors

• Dian-Sheng Yu
• Chun-Wei Chang
• Jhon Jhy Liaw

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260512

Application Date

20220209

Claims (20)

1. 1 . A memory device, comprising: first and second transistors of opposite conductivity types, the first and second transistors sharing a first gate terminal, the first transistor including a first drain/source terminal, the first gate terminal extending longitudinally along a first direction; third and fourth transistors of opposite conductivity types, the third and fourth transistors sharing a second gate terminal, the third transistor including a second source/drain terminal, the second gate terminal extending longitudinally along the first direction; and a first conductive path electrically connected between the first drain/source terminal and the second gate terminal, wherein an extension of a centerline of the first gate terminal along the first direction intersects an edge of the second gate terminal, and wherein the first conductive path includes: a first conductive via electrically connected between the first drain/source terminal and a first track of a first conductive layer; and a second conductive via electrically connected between the first track of the first conductive layer and a first track of a second conductive layer positioned above the first conductive layer.
2. 2 . The memory device of claim 1 , wherein the first conductive path further includes: a third conductive via electrically connected between the second gate terminal and a second track of the first conductive layer; and a fourth conductive via electrically connected between the first track of the second conductive layer and the second track of the first conductive layer.
3. 3 . The memory device of claim 2 , comprising: a second conductive path electrically connected between the second drain/source terminal and the first gate terminal, wherein the second conductive path includes: a fifth conductive via electrically connected between the second drain/source terminal and a third track of the first conductive layer; and a sixth conductive via electrically connected between the third track of the first conductive layer and a second track of the second conductive layer.
4. 4 . The memory device of claim 3 , wherein the second conductive path further includes: a seventh conductive via electrically connected between the first gate terminal and a fourth track of the first conductive layer; and an eighth conductive via electrically connected between the second track of the second conductive layer and the fourth track of the first conductive layer.
5. 5 . The memory device of claim 1 , wherein each of the first transistor and the second transistor is one of a finfet and a stacked nanosheet transistor.
6. 6 . A memory device, comprising: a static random-access memory (SRAM) cell including: a first transistor including a first gate terminal and a drain/source terminal, the first gate terminal extending lengthwise along a first direction; a second transistor including a second gate terminal, the second gate terminal extending lengthwise along the first direction; a conductive path electrically connected between the drain/source terminal and the second gate terminal, the conductive path including: a first conductive via electrically connected between the drain/source terminal and a first track of a first conductive layer; a second conductive via electrically connected between the first track of the first conductive layer and a track of a second conductive layer; a third conductive via electrically connected between the second gate terminal and a first track of a third conductive layer; and a fourth conductive via electrically connected between the first track of the third conductive layer and the track of the second conductive layer, wherein the first transistor is a pull-down (PD) transistor of the SRAM cell and the second transistor is a pull-up (PU) transistor of the SRAM cell, wherein an extension of a centerline of the first gate terminal along the first direction intersects an edge of the second gate terminal, and wherein at least one of a second track of the first conductive layer and a second track of the third conductive layer align with at least one of a power rail and a reference rail.
7. 7 . The memory device of claim 6 , wherein at least one of a third track of the first conductive layer and a third track of the third conductive layer are configured to be directly connected to neighboring logic circuits.
8. 8 . The memory device of claim 6 , wherein the static random-access memory is configured to directly abut neighboring logic devices.
9. 9 . The memory device of claim 6 , comprising a configuration device and a flash memory, wherein the configuration device is configured to load the static random-access memory from the flash memory on power up.
10. 10 . The memory device of claim 6 , wherein the first conductive layer and the third conductive layer are the same conductive layer.
11. 11 . A method for forming a memory device, comprising: providing, in a static random-access memory (SRAM) cell, a first transistor including a first gate terminal and a first drain/source terminal and a second transistor including a second gate terminal, each of the first and second gate terminals extending longitudinally along a first direction, each of the first and second transistors disposed on a straight line extending along the first direction, an extension of a centerline of the first gate terminal along the first direction intersecting an edge of the second gate terminal, wherein the first transistor is a pull-down (PD) transistor of the SRAM cell and the second transistor is a pull-up (PU) transistor of the SRAM cell; connecting, in a first conductive path, a first conductive via between the first drain/source terminal and a first track of a first conductive layer; and connecting a second conductive via between the first track of the first conductive layer and a track of a second conductive layer.
12. 12 . The method of claim 11 , comprising: connecting, in the first conductive path, a third conductive via between the second gate terminal of the second transistor and a first track of a third conductive layer; and connecting a fourth conductive via between the track of the second conductive layer and the first track of the third conductive layer.
13. 13 . The method of claim 11 , comprising: providing, in the static random-access memory, a third transistor including a second drain/source terminal and a fourth transistor including a third gate terminal; connecting, in a second conductive path, a fifth conductive via between the second drain/source terminal and a track of a fourth conductive layer; and connecting a sixth conductive via between the track of the fourth conductive layer and a track of a fifth conductive layer.
14. 14 . The method of claim 11 , comprising manufacturing each of the first transistor, the second transistor, and the first conductive path using extreme ultraviolet lithography.
15. 15 . The method of claim 11 , comprising: connecting at least one of a second track of the first conductive layer and a second track of the third conductive layer directly to neighboring logic devices.
16. 16 . The method of claim 11 , wherein the static random-access memory is manufactured according to logic rules and technology.
17. 17 . The memory device of claim 1 , wherein the first transistor and the second transistor are both disposed on a straight line extending along the first direction.
18. 18 . The memory device of claim 1 , wherein the first, second, third, and fourth transistors are positioned in a same memory cell.
19. 19 . The memory device of claim 1 , wherein the first transistor is a first pull-down (PD) transistor of a memory cell, the second transistor is a first pull-up (PU) transistor of the memory cell, the third transistor is a second PD transistor of the memory cell, and the fourth transistor is a second PU transistor of the memory cell.
20. 20 . The memory device of claim 3 , wherein measured along the first direction a length of the first track of the second conductive layer is longer than a length of the second track of the second conductive layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63/219,939, filed on Jul. 9, 2021, the disclosure of which is incorporated by reference in its entirety. BACKGROUND Typically, a static random-access memory (SRAM) has an array of memory cells that include transistors connected between an upper reference potential and a lower reference potential, such that one of two storage nodes stores information to be stored and the other storage node stores the complementary information. One SRAM memory cell arrangement includes six transistors, where each bit of information is stored on four of the transistors that form two cross-coupled inverters. The other two transistors are connected to the memory cell word line to control access to the memory cell during read and write operations by selectively connecting the memory cell to a bit line BL and a bit line bar, i.e., an inverted bit line, BLB. Since SRAM is volatile memory, data is lost when power is removed from the SRAM. As a result, SRAM-based field programmable gate array (FPGA) devices include additional components, such as a configuration device and non-volatile memory, to store data from the SRAM at power down and load data into the SRAM at power up. SRAM-based FPGA devices continue being developed to improve performance and lower costs. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. In addition, the drawings are illustrative as examples of embodiments of the disclosure and are not intended to be limiting. FIG. 1 is a diagram schematically illustrating an SRAM-based FPGA device, in accordance with some embodiments. FIG. 2 is a block diagram schematically illustrating an SRAM, in accordance with some embodiments. FIG. 3A is a diagram schematically illustrating one of the SRAM memory cells, in accordance with some embodiments. FIG. 3B is a diagram schematically illustrating a finfet cell that can be used in manufacturing the SRAM memory cell of FIG. 3A, in accordance with some embodiments. FIG. 3C is a diagram schematically illustrating a stacked nanosheet transistor that can be used in manufacturing the SRAM memory cell of FIG. 3A, in accordance with some embodiments. FIG. 4 is a block diagram schematically illustrating an example of a computer system configured for designing and manufacturing the SRAM-based FPGA devices of this disclosure, in accordance with some embodiments. FIG. 5 is a block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith, in accordance with some embodiments. FIG. 6 is a diagram schematically illustrating a 6T SRAM circuit layout, referred to herein as cell A, in accordance with some embodiments. FIG. 7 is a diagram schematically illustrating two conductive paths that cross-couple the first and second inverters in the 6T SRAM circuit layout (cell A) of the 6T SRAM memory cell, in accordance with some embodiments. FIG. 8 is a diagram schematically illustrating a perspective cross-sectional view of the connections through the MEOL vias and the BEOL conductive layers in the first conductive path, in accordance with some embodiments. FIG. 9 is a diagram schematically illustrating another 6T SRAM circuit layout, referred to herein as cell B, in accordance with some embodiments. FIG. 10 is a diagram schematically illustrating two conductive paths that cross-couple the first and second inverters in the 6T SRAM circuit layout (cell B) of the 6T SRAM memory cell, in accordance with some embodiments. FIG. 11 is a diagram schematically illustrating the 6T SRAM circuit layout (cell A) including a VDD power rail and a VSS reference rail, in accordance with some embodiments. FIG. 12 is a diagram schematically illustrating the 6T SRAM circuit layout (cell B) including a VDD power rail and a VSS reference rail, in accordance with some embodiments. FIG. 13 is a diagram schematically illustrating the 6T SRAM circuit layout (cell A) connected to a peripheral logic circuit, in accordance with some embodiments. FIG. 14 is a diagram schematically illustrating the 6T SRAM circuit layout (cell B) connected to a peripheral logic circuit, in accordance with some embodiments. FIG. 15 is a diagram schematically illustrating a method of connecting transistors in an SRAM, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are