US-12628328-B2 - Memory devices having vertical transistors and methods for forming the same

Abstract

A semiconductor device and methods for forming the same are provided. The method includes: forming a plurality of first trenches having a first width during forming a plurality of grooves having a second width less than the first width, each of the plurality of first trenches and the plurality of grooves extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer, the plurality of first trenches and the plurality of grooves being alternatively arranged along a second lateral direction different from the first lateral direction; forming a spacer in each groove, where the spacer is laterally extending along the first lateral direction; and forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction.

Inventors

• Wei Liu
• Hongbin Zhu
• Yanhong Wang
• Zichen LIU

Assignees

• YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260512

Application Date

20230717

Claims (20)

1. 1 . A method for forming a semiconductor structure, comprising: forming a plurality of first trenches having a first width during forming a plurality of grooves having a second width less than the first width, each of the plurality of first trenches and the plurality of grooves extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer, the plurality of first trenches and the plurality of grooves being alternatively arranged along a second lateral direction different from the first lateral direction; forming a spacer in each groove, wherein the spacer is laterally extending along the first lateral direction; depositing at least one dielectric material to form a bottom dielectric structure located in a lower portion of each first trench; oxidizing portions of the semiconductor layer to form gate dielectric layers on sidewalls of each first trench; and forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction.
2. 2 . The method of claim 1 , wherein: each first trench has a first depth; and each groove has a second depth less than the first depth.
3. 3 . The method of claim 1 , wherein each disconnected conductive structure extends vertically along a corresponding one of the gate dielectric layers.
4. 4 . The method of claim 1 , further comprising: before forming the plurality of first trenches and grooves, forming a plurality of second trenches each extending laterally along the second lateral direction and vertically in the upper portion of the semiconductor layer, wherein the second lateral direction being perpendicular to the first lateral direction.
5. 5 . A method for forming an array of memory cells, comprising: forming a plurality of grooves having a second width, each groove extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer; forming a sacrificial layer in each groove; forming a cap layer to alternatively cover the sacrificial layer in a first subset of grooves having a first parity; removing the sacrificial layer in a second subset of grooves having a second parity that are uncovered by the cap layer, and enlarging each of the second subset of grooves to from a plurality of first trenches each having a first width greater than the second width; depositing at least one dielectric material to form a bottom dielectric structure located in a lower portion of each first trench; oxidizing portions of the semiconductor layer to form gate dielectric layers on sidewalls of each first trench; and forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction.
6. 6 . The method of claim 5 , wherein: each first trench has a first depth; and each groove has a second depth less than the first depth.
7. 7 . The method of claim 5 , wherein each disconnected conductive structure extends vertically along a corresponding one of the gate dielectric layers.
8. 8 . The method of claim 5 , further comprising: before forming the plurality of grooves, forming a plurality of second trenches each extending laterally along a second lateral direction and vertically in the upper portion of the semiconductor layer; wherein the second lateral direction being perpendicular to the first lateral direction.
9. 9 . The method of claim 8 , further comprising: after forming the plurality of first trenches, depositing an initial dielectric layer in the plurality of first trenches; and remove an upper portion of the initial dielectric layer to form the bottom dielectric structure.
10. 10 . A method for forming a semiconductor structure, comprising: during forming a plurality of first trenches having a first width forming a plurality of grooves having a second width less than the first width, each of the plurality of first trenches and the plurality of grooves extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer, the plurality of first trenches and the plurality of grooves being alternatively arranged along a second lateral direction different from the first lateral direction; forming a spacer in each groove, wherein the spacer is laterally extending along the first lateral direction; depositing at least one dielectric material to form a bottom dielectric structure located in a lower portion of each first trench; oxidizing portions of the semiconductor layer to form gate dielectric layers on sidewalls of each first trench; and forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction.
11. 11 . The method of claim 10 , wherein: each first trench has a first depth; and each groove has a second depth less than the first depth.
12. 12 . The method of claim 10 , wherein each disconnected conductive structure extends vertically along a corresponding one of the gate dielectric layers.
13. 13 . The method of claim 10 , further comprising: before forming the plurality of first trenches and grooves, forming a plurality of second trenches each extending laterally along the second lateral direction and vertically in the upper portion of the semiconductor layer; wherein the second lateral direction being perpendicular to the first lateral direction.
14. 14 . The method of claim 10 , wherein forming the spacer comprises: depositing a dielectric material in the plurality of first trenches and the plurality of grooves.
15. 15 . The method of claim 13 , wherein after forming the plurality of first trenches, the method further comprises: depositing an initial dielectric layer in the plurality of first trenches; and remove an upper portion of the initial dielectric layer to form the bottom dielectric structure.
16. 16 . The method of claim 15 , wherein forming the two disconnected conductive structures in each first trench comprises: forming a continuous conductive structure in each first trench covering sidewalls of each first trench and a top surface of the bottom dielectric structure; and removing a bottom portion of the continuous conductive structure on the top surface of the bottom dielectric structure to separate the continuous conductive structure into the two disconnected conductive structures.
17. 17 . The method of claim 16 , further comprising: before forming the continuous conductive structure, oxidizing sidewalls of a plurality of semiconductor bodies separated by the plurality of first trenches, second trenches, and grooves, to form the gate dielectric layer on sidewalls of each first trench.
18. 18 . The method of claim 17 , wherein forming the continuous conductive structure comprises: forming a first conductive layer to cover the gate dielectric layer and the bottom dielectric structure; and forming a second conductive layer to cover the first conductive layer.
19. 19 . The method of claim 16 , wherein removing the bottom portion of the continuous conductive structure comprises: performing a punch-down etch or a dry etching process to remove the bottom portion of the continuous conductive structure to expose the bottom dielectric structure.
20. 20 . The method of claim 16 , further comprising forming an isolating structure extending along the first lateral direction between the disconnected conductive structures in each first trench.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of Internal Application No. PCT/CN2023/094203, filed May 15, 2023, entitled “MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME,” which claims the benefit of priorities to U.S. Provisional Application No. 63/343,848, filed on May 19, 2022, and to U.S. Provisional Application No. 63/351,604, filed on Jun. 13, 2022, all of which are hereby incorporated by reference in their entireties. BACKGROUND The present disclosure relates to memory devices and fabrication methods thereof. Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral circuits for facilitating operations of the memory array. SUMMARY In one aspect, a method for forming a semiconductor device is disclosed. The method includes: forming a plurality of first trenches having a first width during forming a plurality of grooves having a second width less than the first width, each of the plurality of first trenches and the plurality of grooves extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer, the plurality of first trenches and the plurality of grooves being alternatively arranged along a second lateral direction different from the first lateral direction; forming a spacer in each groove, where the spacer is laterally extending along the first lateral direction; and forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction. In another aspect, another method for forming a semiconductor device is disclosed. The method includes: forming a plurality of first trenches having a first width during forming a plurality of grooves having a second width less than the first width, each of the plurality of first trenches and the plurality of grooves extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer, the plurality of first trenches and the plurality of grooves being alternatively arranged along a second lateral direction different from the first lateral direction; filling each first trench and each groove with a sacrificial material; replacing an upper portion of the sacrificial material in each groove with a cap layer; removing the sacrificial material in each first trench; and forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction. In yet another aspect, another method for forming a semiconductor device is disclosed. The method includes: forming a plurality of grooves having a second width, each groove extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer; forming a sacrificial layer in each groove; forming a cap layer to alternatively cover the sacrificial layer in a first subset of grooves having a first parity; removing the sacrificial layer in a second subset of grooves having a second parity that are uncovered by the cap layer, and enlarging each of the second subset of grooves to from a plurality of first trenches each having a first width greater than the second width; and forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction. In yet another aspect, another method for forming a semiconductor device is disclosed. The method includes: during forming a plurality of first trenches having a first width forming a plurality of grooves having a second width less than the first width, each of the plurality of first trenches and the plurality of grooves extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer, the plurality of first trenches and the plurality of grooves being alternatively arranged along a second lateral direction different from the first lateral direction; forming a spacer in each groove, where the spacer is laterally extending along the first lateral direction; and forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction. In still another aspect, a semiconductor device is disclosed. The semiconductor device includes an array of vertical transistors each having a semiconductor body ex