US-12628329-B2 - Semiconductor memory device

US12628329B2US 12628329 B2US12628329 B2US 12628329B2US-12628329-B2

Abstract

A semiconductor memory device includes a substrate including a first region and a second region arranged in a first direction, and first electrodes arranged in a second direction. The first electrodes each include a pair of first parts disposed in the first region and arranged in a third direction, and a second part disposed in the second region and electrically connected to the first parts. The device includes first wirings arranged along one of the first parts, first semiconductor layers opposed to the one of the first parts and connected to the first wirings, first memory portions electrically connected to the first wirings via the first semiconductor layers, second wirings arranged along the other of the first parts, second semiconductor layers opposed to the other of the first parts and connected to the second wirings, and second memory portions electrically connected to the second wirings via the second semiconductor layers.

Inventors

Naomi Ito
Koichi Kishi

Assignees

KIOXIA CORPORATION

Dates

Publication Date: 20260512
Application Date: 20221216
Priority Date: 20211228

Claims (9)

1 . A semiconductor memory device comprising: a substrate including a first region and a second region arranged in a first direction; a plurality of first electrodes arranged in a second direction intersecting with a surface of the substrate, and each including: a pair of first parts disposed in the first region, extending in the first direction, and arranged in a third direction intersecting with the first direction and the second direction; and a second part disposed in the second region, extending in the third direction, having an L-shape, and electrically connected to the pair of first parts; a plurality of first wirings arranged in the first direction along a plurality of ones of the pairs of first parts of the plurality of first electrodes, and extending in the second direction; a plurality of first semiconductor layers arranged in the first direction and the second direction corresponding to the plurality of the ones of the pairs of first parts of the plurality of first electrodes and the plurality of first wirings, opposed to the plurality of the ones of the pairs of first parts of the plurality of first electrodes, and connected to the plurality of first wirings; a plurality of first memory portions electrically connected to the plurality of first wirings via the plurality of first semiconductor layers; a plurality of second wirings arranged in the first direction along a plurality of others of the pairs of first parts of the plurality of first electrodes, and extending in the second direction; a plurality of second semiconductor layers arranged in the first direction and the second direction corresponding to the plurality of the other of the pairs of first parts of the plurality of first electrodes and the plurality of second wirings, opposed to the plurality of the other of the pairs of first parts of the plurality of first electrodes, and connected to the plurality of second wirings; and a plurality of second memory portions electrically connected to the plurality of second wirings via the plurality of second semiconductor layers.
2 . The semiconductor memory device according to claim 1 , further comprising: a plurality of first contact electrodes disposed in the second region, extending in the second direction, arranged in the third direction, and connected to the respective plurality of first electrodes; a plurality of third wirings disposed in the second region, extending in the first direction, arranged in the third direction, and connected to the respective plurality of first contact electrodes; and a fourth wiring disposed in the first region, extending in the third direction, and connected to one of the plurality of first wirings.
3 . The semiconductor memory device according to claim 1 , further comprising: a plurality of second electrodes arranged in the second direction, aligned with the plurality of first electrodes in the third direction, and each including: a third part disposed in the first region, and extending in the first direction; and a fourth part disposed in the second region, extending in the third direction, electrically connected to the third part, and the first part and the third part being disposed between the second part and the fourth part in the third direction; a plurality of fifth wirings arranged in the first direction along a plurality of the third parts of the plurality of second electrodes, and extending in the second direction; a plurality of third semiconductor layers arranged in the first direction and the second direction corresponding to the plurality of the third parts of the plurality of second electrodes and the plurality of fifth wirings, opposed to the plurality of the third parts of the plurality of second electrodes, and electrically connected to the plurality of fifth wirings; a plurality of third memory portions electrically connected to the plurality of fifth wirings via the plurality of third semiconductor layers; and a plurality of fourth wirings and a plurality of sixth wirings alternately arranged in the first direction in the first region, extending in the third direction, the plurality of fourth wirings being electrically connected to the plurality of first wirings, and the plurality of sixth wirings being electrically connected to the plurality of fifth wirings.
4 . The semiconductor memory device according to claim 1 , wherein the plurality of memory portions each include a capacitor.
5 . The semiconductor memory device according to claim 1 , wherein the one of the pair of first parts is continuous to the other of the pair of first parts via the second part.
6 . The semiconductor memory device according to claim 1 , further comprising: a plurality of second electrodes arranged in the second direction, aligned with the plurality of first electrodes in the third direction, and each including: a third part disposed in the first region, and extending in the first direction; and a fourth part disposed in the second region, extending in the third direction, electrically connected to the third part, and the first part and the third part being disposed between the second part and the fourth part in the third direction; a plurality of fifth wirings arranged in the first direction along a plurality of the third parts of the plurality of second electrodes, and extending in the second direction; a plurality of third semiconductor layers arranged in the first direction and the second direction corresponding to the plurality of the third parts of the plurality of second electrodes and the plurality of fifth wirings, opposed to the plurality of the third parts of the plurality of second electrodes, and electrically connected to the plurality of fifth wirings; a plurality of third memory portions electrically connected to the plurality of fifth wirings via the plurality of third semiconductor layers; and a sense amplifier circuit electrically connected to one of the first wirings and one of the fifth wirings, wherein the sense amplifier circuit includes a first inverter and a second inverter, the one of the plurality of first wirings is connected to an input terminal of the first inverter and an output terminal of the second inverter, and the one of the plurality of fifth wirings is connected to an output terminal of the first inverter and an input terminal of the second inverter.
7 . The semiconductor memory device according to claim 6 , wherein the plurality of first electrodes are electrically independent from the plurality of second electrodes.
8 . The semiconductor memory device according to claim 1 , wherein the first region includes a plurality of sense unit regions arranged in the first direction corresponding to the plurality of first wirings, each of the plurality of sense unit regions includes a sense amplifier circuit, and the plurality of sense unit regions are disposed in positions that overlap the plurality of first wirings when viewed from the second direction.
9 . The semiconductor memory device according to claim 1 , wherein the second parts have protruding part which protrudes in the third direction from a position of an edge of the pair of first parts, the edge extending in the first direction.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of Japanese Patent Application No. 2021-214720, filed on Dec. 28, 2021, the entire contents of which are incorporated herein by reference. BACKGROUND Field Embodiments described herein relate generally to a semiconductor memory device. Description of the Related Art In accordance with an increasing high integration of a semiconductor memory device, a study for converting the semiconductor memory device into a three-dimensional form has been in progress. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram illustrating an exemplary configuration of a semiconductor memory device according to a first embodiment; FIG. 2 is a schematic circuit diagram illustrating a part of the configuration of the semiconductor memory device; FIG. 3 is a schematic circuit diagram illustrating a part of the configuration of the semiconductor memory device; FIG. 4 is a schematic plan view illustrating a part of the configuration of the semiconductor memory device; FIG. 5 is a schematic perspective view illustrating a part of the configuration of the semiconductor memory device; FIG. 6 is a schematic plan view illustrating a part of the configuration of the semiconductor memory device; FIG. 7 is a schematic plan view illustrating a part of the configuration of the semiconductor memory device; FIG. 8 is a schematic plan view illustrating a part of the configuration of the semiconductor memory device; FIG. 9 is a schematic plan view illustrating a part of the configuration of the semiconductor memory device; FIG. 10 is a schematic plan view illustrating a part of the configuration of the semiconductor memory device; FIG. 11 is a schematic plan view illustrating a part of the configuration of the semiconductor memory device; FIG. 12 is a schematic cross-sectional view illustrating a part of the configuration of the semiconductor memory device; FIG. 13 is a schematic cross-sectional view illustrating a part of the configuration of the semiconductor memory device; FIG. 14 is a schematic cross-sectional view illustrating a part of the configuration of the semiconductor memory device; FIG. 15 is a schematic cross-sectional view illustrating a part of the configuration of the semiconductor memory device; FIG. 16 is a schematic cross-sectional view for describing a manufacturing method of the semiconductor memory device according to the first embodiment; FIG. 17 is a schematic cross-sectional view for describing the manufacturing method; FIG. 18 is a schematic cross-sectional view for describing the manufacturing method; FIG. 19 is a schematic cross-sectional view for describing the manufacturing method; FIG. 20 is a schematic cross-sectional view for describing the manufacturing method; FIG. 21 is a schematic cross-sectional view for describing the manufacturing method; FIG. 22 is a schematic cross-sectional view for describing the manufacturing method; FIG. 23 is a schematic cross-sectional view for describing the manufacturing method; FIG. 24 is a schematic cross-sectional view for describing the manufacturing method; FIG. 25 is a schematic cross-sectional view for describing the manufacturing method; FIG. 26 is a schematic cross-sectional view for describing the manufacturing method; FIG. 27 is a schematic cross-sectional view for describing the manufacturing method; FIG. 28 is a schematic cross-sectional view for describing the manufacturing method; FIG. 29 is a schematic cross-sectional view for describing the manufacturing method; FIG. 30 is a schematic cross-sectional view for describing the manufacturing method; FIG. 31 is a schematic cross-sectional view for describing the manufacturing method; FIG. 32 is a schematic cross-sectional view for describing the manufacturing method; FIG. 33 is a schematic cross-sectional view for describing the manufacturing method; FIG. 34 is a schematic cross-sectional view for describing the manufacturing method; FIG. 35 is a schematic cross-sectional view for describing the manufacturing method; FIG. 36 is a schematic cross-sectional view for describing the manufacturing method; FIG. 37 is a schematic cross-sectional view for describing the manufacturing method; FIG. 38 is a schematic cross-sectional view for describing the manufacturing method; FIG. 39 is a schematic cross-sectional view for describing the manufacturing method; FIG. 40 is a schematic cross-sectional view for describing the manufacturing method; FIG. 41 is a schematic cross-sectional view for describing the manufacturing method; FIG. 42 is a schematic cross-sectional view for describing the manufacturing method; FIG. 43 is a schematic cross-sectional view for describing the manufacturing method; FIG. 44 is a schematic cross-sectional view for describing the manufacturing method; FIG. 45 is a schematic cross-sectional view for describing the manufacturing method; FIG. 46 is a schematic cross-sectional view for describing t