US-12628330-B2 - Semiconductor device

Abstract

A semiconductor device includes a substrate having an active area and a non-active area. An extra pad layer is disposed on the active area of the substrate. A first contact layer is disposed in a contact hole defined inside the substrate from a surface of the extra pad layer. A first silicide layer is disposed on both sidewalls of the first contact layer. A buried insulating layer is buried in the contact hole at lateral sides of the first contact layer and the first silicide layer. A second silicide layer is disposed on an upper surface and sidewalls of the extra pad layer. A second contact layer is on the buried insulating layer and the second silicide layer and is in direct contact with the second silicide layer.

Inventors

• JUNHYEOK AHN
• Hyosub Kim
• Sohyun Park

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20221201

Priority Date

20220120

Claims (20)

1. 1 . A semiconductor device comprising: a substrate having an active area and a non-active area; an extra pad layer disposed on the active area of the substrate; a first contact layer disposed in a contact hole defined inside the substrate from a surface of the extra pad layer; a first silicide layer disposed on both sidewalls of the first contact layer; a buried insulating layer buried in the contact hole at lateral sides of the first contact layer and the first silicide layer; a second silicide layer disposed on an upper surface and sidewalk of the extra pad layer; and a second contact layer on the buried insulating layer and the second silicide layer and in direct contact with the second silicide layer.
2. 2 . The semiconductor device of claim 1 , wherein the first contact layer and the first silicide layer are first contact plugs in contact with the active area of the substrate.
3. 3 . The semiconductor device of claim 1 , wherein the first contact layer comprises a protrusion part protruding from the upper surface of the extra pad layer.
4. 4 . The semiconductor device of claim 1 , wherein the second silicide layer is disposed on an entirety of the upper surface and sidewalls of the extra pad layer.
5. 5 . The semiconductor device of claim 1 , wherein the second silicide layer is disposed inside a portion of the upper surface of the extra pad layer, and is disposed on an entirety of the sidewalls of the extra pad layer.
6. 6 . The semiconductor device of claim 1 , wherein the first silicide layer is composed of a same material as the second silicide layer.
7. 7 . The semiconductor device of claim 1 , wherein: a recess hole exposing the second silicide layer is further defined on an upper surface of the buried insulating layer; and the second contact layer is buried in the recess hole.
8. 8 . The semiconductor device of claim 1 , wherein the buried insulating layer comprises a liner layer in direct contact with the first silicide layer and the second silicide layer in the contact hole, and a liner buried layer filling the contact hole on the liner layer.
9. 9 . The semiconductor device of claim 1 , wherein the second contact layer is a second contact plug contacting the active area of the substrate through the second silicide layer and the extra pad layer.
10. 10 . A semiconductor device comprising: a substrate having an active area and a non-active area; an extra pad layer disposed on the active area of the substrate; a first contact silicide layer disposed in a contact hole defined inside the substrate from a surface of the extra pad layer; a buried insulating layer buried in the contact hole on lateral sides of the first contact silicide layer; a second silicide layer disposed on an upper surface and sidewalls of the extra pad layer; and a second contact layer on the buried insulating layer and the second silicide layer and in direct contact with the second silicide layer.
11. 11 . The semiconductor device of claim 10 , wherein: the first contact silicide layer is a first contact plug in contact with the active area of the substrate; and the second contact layer is a second contact plug contacting the active area of the substrate through the second silicide layer and the extra pad layer.
12. 12 . The semiconductor device of claim 10 , wherein the first contact silicide layer is composed of a metal silicide layer.
13. 13 . The semiconductor device of claim 10 , wherein the first contact silicide layer is composed of a same material as the second silicide layer.
14. 14 . The semiconductor device of claim 10 , wherein the first contact silicide layer comprises a protrusion part protruding from the upper surface of the extra pad layer.
15. 15 . The semiconductor device of claim 10 , wherein the second silicide layer is disposed inside a portion of the upper surface of the extra pad layer, and is disposed on an entirety of the sidewalls of the extra pad layer.
16. 16 . A semiconductor device comprising: a substrate having an active area and a non-active area; an extra pad layer disposed on the active area of the substrate; a pad isolation insulating layer disposed on the non-active area of the substrate and insulating the extra pad layer; a first contact layer disposed in a contact hole defined inside the substrate from a surface of the extra pad layer; a first silicide layer disposed on both sidewalls of the first contact layer; a first conductive layer disposed on the first contact layer and the first silicide layer; a buried insulating layer buried in the contact hole at lateral sides of the first contact layer and the first silicide layer; a second silicide layer disposed on an upper surface and sidewalls of the extra pad layer; a second contact layer on the buried insulating layer and the second silicide layer and in direct contact with the second silicide layer; and a second conductive layer disposed on the pad isolation insulating layer and insulated from the second contact layer.
17. 17 . The semiconductor device of claim 16 , wherein the first contact layer extends in a direction perpendicular to a surface of the substrate and comprises a protrusion part protruding from the upper surface of the extra pad layer.
18. 18 . The semiconductor device of claim 16 , wherein: an upper width of the first contact layer is less than a width of the first conductive layer; and the upper width of the first silicide layer is equal to the width of the first conductive laver.
19. 19 . The semiconductor device of claim 16 , wherein: a buffer insulating layer is further disposed on the pad isolation insulating layer; and the second conductive layer is disposed on the buffer insulating layer.
20. 20 . The semiconductor device of claim 16 , wherein: the first conductive layer and the second conductive layer are a first conductive line and a second conductive line extending in a first direction on the substrate, respectively; the first contact layer and the first silicide layer are disposed under the first conductive line; and the second contact layer is disposed between the first conductive line and the second conductive line.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 U.S.C, § 119 to Korean Patent Application No. 10-2022-0008690, filed on Jan. 20, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein. 1. TECHNICAL FIELD The present inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device capable of increasing resistance characteristics and increasing integration. 2. DISCUSSION OF RELATED ART As semiconductor devices are increasingly downscaled, the size of a circuit pattern for the semiconductor device is further reduced. In addition, as the integration level of semiconductor devices has increased, the line width of a conductive line, for example, a bit line, has decreased. Accordingly, the difficulty of a process of forming a contact between conductive lines has increased, and it is becoming more difficult to increase resistance characteristics and the integration level of the semiconductor device. SUMMARY The present inventive concept provides a semiconductor device capable of increasing resistance characteristics and the integration level of the semiconductor device. According to an embodiment of the present inventive concept, a semiconductor device includes a substrate having an active area and a non-active area. An extra pad layer is disposed on the active area of the substrate. A first contact layer is disposed in a contact hole defined inside the substrate from a surface of the extra pad layer. A first silicide layer is disposed on both sidewalk of the first contact layer. A buried insulating layer is buried in the contact hole at lateral sides of the first contact layer and the first silicide layer. A second silicide layer is disposed on an upper surface and sidewalk of the extra pad layer. A second contact layer is on the buried insulating layer and the second silicide layer and is in direct contact with the second silicide layer. According to an embodiment of the present inventive concept, a semiconductor device includes a substrate having an active area and a non-active area. An extra pad layer is disposed on the active area of the substrate. A first contact silicide layer is disposed in a contact hole defined inside the substrate from a surface of the extra pad layer. A buried insulating layer is buried in the contact holes on lateral sides of the first contact silicide layer. A second silicide layer is disposed on an upper surface and sidewalls of the extra pad layer. A second contact layer is on the buried insulating layer and the second silicide layer and in direct contact with the second silicide layer. According to an embodiment of the present inventive concept, a semiconductor device includes a substrate having an active area and a non-active area. An extra pad layer is disposed on the active area of the substrate. A pad isolation insulating layer is disposed on the non-active area of the substrate and insulating the extra pad layer. A first contact layer is disposed in a contact hole defined inside the substrate from a surface of the extra pad layer, A first silicide layer is disposed on both sidewalls of the first contact layer. A first conductive layer is disposed on the first contact layer and the first silicide layer. A buried insulating layer is buried in the contact hole at lateral sides of the first contact layer and the first silicide layer. A second silicide layer is disposed on an upper surface and sidewalls of the extra pad layer. A second contact layer is on the buried insulating layer and the second silicide layer and in direct contact with the second silicide layer. A second conductive layer is disposed on the pad isolation insulating layer and insulated from the second contact layer. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: FIG. 1 is a schematic layout diagram of a semiconductor device according to an embodiment of the present inventive concept; FIG. 2 is a schematic layout diagram of a semiconductor device according to an embodiment of the present inventive concept; FIG. 3A is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present inventive concept; FIG. 3B is an enlarged cross-sectional view of a portion EN1 of FIG. 3A according to an embodiment of the present inventive concept; FIG. 4 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present inventive concept; FIG. 5 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present inventive concept: FIG. 6 is an enlarged cross-sectional view of a portion EN2 of FIG. 5 according to an embodiment of the present inventive concept; FIG. 7 is a cross-sectional view of a main part of a