US-12628331-B2 - Semiconductor memory device having stacked word lines including sub-gate electrodes

Abstract

A semiconductor memory device may include a lower layer including a first region and a second region, the lower layer extending in a first direction and a second direction perpendicular to the first direction, and a stack including word lines and interlayer insulating patterns, which are alternatingly stacked in a third direction perpendicular to the first direction and the second direction, the stack having a staircase structure on the second region. The word lines may extend from the first region to the second region in the first direction. Each of the word lines may include sub-gate electrodes, which extend parallel to each other in the first region, and a word line pad, which is connected in common to the sub-gate electrodes in the second region.

Inventors

• Hyungeun CHOI
• Kiseok LEE
• Haejoon LEE
• Seungjae Jung

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20230109

Priority Date

20220328

Claims (19)

1. 1 . A semiconductor memory device, comprising: a lower layer including a first region and a second region, the lower layer extending in a first direction and a second direction perpendicular to the first direction, each of the first and second directions being parallel to a top surface of the lower layer; and a stack including word lines and interlayer insulating patterns, which are alternatingly stacked in a third direction perpendicular to the top surface of the lower layer, the stack having a staircase structure on the second region, wherein the word lines extend lengthwise from the first region to the second region in the first direction, and wherein each of the word lines comprises sub-gate electrodes, which are stacked in the third direction and extend parallel to each other in the first region, and a word line pad, which is connected in common to the sub-gate electrodes in the second region.
2. 2 . The semiconductor memory device of claim 1 , wherein, in each of the word lines, a thickness of the word line pad in the third direction is larger than a thickness of each of the sub-gate electrodes in the third direction.
3. 3 . The semiconductor memory device of claim 1 , further comprising a gate insulating layer disposed between the interlayer insulating patterns and the sub-gate electrodes.
4. 4 . The semiconductor memory device of claim 1 , further comprising: line insulating patterns, which are disposed at both sides of the stack and extend lengthwise in the first direction to be parallel to the stack, wherein each of the line insulating patterns has a staircase structure on the second region.
5. 5 . The semiconductor memory device of claim 4 , wherein each of the line insulating patterns has a decreasing width in the second direction, as a distance from the first region increases.
6. 6 . The semiconductor memory device of claim 1 , wherein the word line pads have widths in the second direction that decrease as a distance from the first region increases.
7. 7 . The semiconductor memory device of claim 1 , further comprising: channel patterns disposed between the sub-gate electrodes of each of the word lines and spaced apart from each other in the first direction; bit lines, which extend in the third direction to cross the word lines in the first region and are connected to first end portions of the channel patterns; and data storage elements connected to second end portions of the channel patterns.
8. 8 . The semiconductor memory device of claim 7 , wherein, in each of the word lines, the word line pad comprises a protruding portion that protrudes into a region between the sub-gate electrodes.
9. 9 . A semiconductor memory device, comprising: a lower layer including a first region and a second region, the lower layer extending in a first direction and a second direction perpendicular to the first direction, each of the first and second directions being parallel to a top surface of the lower layer; a stack including word lines and interlayer insulating patterns, which are alternatingly stacked in a third direction perpendicular to the top surface of the lower layer, each of the word lines having a word line pad in the second region, and the stack having a staircase structure in the second region; channel patterns provided to cross the word lines and stacked in the third direction; a bit line extending lengthwise in the third direction to cross the word lines, in the first region, the bit line connected to first end portions of the channel patterns; data storage elements provided in the first region and connected to second end portions of the channel patterns; and cell contact plugs provided in the second region and respectively coupled to the word line pads, wherein a thickness, in the third direction, of each of the word lines in the first region is different from a thickness of the each of the word lines in the second region.
10. 10 . The semiconductor memory device of claim 9 , further comprising a gate insulating layer, which is disposed in the first region and between the interlayer insulating patterns and the word lines and between the channel patterns and the word lines.
11. 11 . The semiconductor memory device of claim 10 , wherein, in the second region, each of the word line pads has a top surface and a bottom surface, which are in contact with the interlayer insulating patterns.
12. 12 . The semiconductor memory device of claim 9 , wherein the word lines comprise first and second word lines, which are alternately disposed in the third direction, and wherein in the second region, the word line pads of the first word lines have side surfaces which are aligned to side surfaces of the second word lines therebelow.
13. 13 . The semiconductor memory device of claim 9 , further comprising: line insulating patterns, which are disposed at both sides of the stack and extend lengthwise in the first direction to be parallel to the stack, wherein the line insulating patterns are provided to have the same staircase structure as the stack, in the second region.
14. 14 . A semiconductor memory device, comprising: a cell array structure including a memory cell array and first bonding pads connected to the memory cell array, the memory cell array including memory cells, which are three-dimensionally arranged; and a peripheral circuit structure including peripheral circuits and second bonding pads, which are connected to the peripheral circuits and are bonded to the first bonding pads, wherein the cell array structure comprises: a lower layer including a first region and a second region, the lower layer extending in a first direction and a second direction perpendicular to the first direction, each of the first and second directions being parallel to a top surface of the lower layer; a stack including word lines and interlayer insulating layers, which are alternately stacked in a third direction perpendicular to the top surface of the lower layer, each of the word lines comprising sub-gate electrodes, which are stacked in the third direction and extend parallel to each other in the first region, and a word line pad, which is connected in common to the sub-gate electrodes in the second region, and the stack having a staircase structure in the second region; bit lines extending lengthwise along the third direction to cross the word lines; and cell contact plugs provided on the second region and respectively coupled to the word line pads, the cell contact plugs connected to the first bonding pads.
15. 15 . The semiconductor memory device of claim 14 , wherein the word lines extend lengthwise from the first region to the second region in the first direction, and wherein, in each of the word lines, a thickness of the word line pad in the third direction is larger than a thickness of each of the sub-gate electrodes in the third direction.
16. 16 . The semiconductor memory device of claim 14 , further comprising: channel patterns, which are provided in the first region and are stacked in the third direction; and data storage elements connected to first end portions of the channel patterns.
17. 17 . The semiconductor memory device of claim 16 , further comprising a gate insulating layer disposed between the sub-gate electrodes and the channel patterns.
18. 18 . The semiconductor memory device of claim 14 , wherein each of the word line pads comprises a protruding portion, which is disposed between the sub-gate electrodes.
19. 19 . The semiconductor memory device of claim 14 , further comprising: line insulating patterns, which are disposed at both sides of the stack and extend lengthwise in the first direction parallel to the stack, wherein the line insulating patterns have substantially the same staircase structure as the stack, in the second region.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0038356, filed on Mar. 28, 2022, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference. BACKGROUND The present disclosure relates to a semiconductor device and a semiconductor memory device including the same, and in particular, to a three-dimensional semiconductor memory device with an improved reliability property and an increased integration density. Higher integration of semiconductor devices is required to satisfy consumer demands for superior performance and inexpensive prices. In the case of semiconductor devices, since their integration is an important factor in determining product prices, increased integration is especially required. In the case of two-dimensional or planar semiconductor devices, since their integration is mainly determined by the area occupied by a unit memory cell, integration is greatly influenced by the level of a fine pattern forming technology. However, the extremely expensive process equipment needed to increase pattern fineness sets a practical limitation on increasing integration for two-dimensional or planar semiconductor devices. Thus, three-dimensional semiconductor memory devices including three-dimensionally arranged memory cells have recently been proposed. SUMMARY An embodiment of the inventive concept provides a semiconductor memory device with an improved reliability property and an increased integration density. According to an embodiment of the inventive concept, a semiconductor memory device may include a lower layer including a first region and a second region, the lower layer extending in a first direction and a second direction perpendicular to the first direction, and a stack including word lines and interlayer insulating patterns, which are alternatingly stacked in a third direction perpendicular to the first direction and the second direction, the stack having a staircase structure on the second region. The word lines may extend from the first region to the second region in a first direction. Each of the word lines may include sub-gate electrodes, which extend parallel to each other in the first region, and a word line pad, which is connected in common to the sub-gate electrodes in the second region. According to an embodiment of the inventive concept, a semiconductor memory device may include a lower layer including a first region and a second region, the lower layer extending in a first direction and a second direction perpendicular to the first direction, a stack including word lines and interlayer insulating patterns, which are alternatingly stacked in a third direction perpendicular to the first direction and the second direction, each of the word lines having a word line pad in the second region, and the stack having a staircase structure in the second region, channel patterns provided to cross the word lines and stacked in the third direction, a bit line extending along the third direction to cross the word lines, in the first region, the bit line connected to first end portions of the channel patterns, data storage elements provided in the first region and connected to second end portions of the channel patterns, and cell contact plugs provided in the second region and respectively coupled to the word line pads. According to an embodiment of the inventive concept, a semiconductor memory device may include a cell array structure including a memory cell array and first bonding pads connected to the memory cell array, the memory cell array including memory cells, which are three-dimensionally arranged, and a peripheral circuit structure including peripheral circuits and second bonding pads, which are connected to the peripheral circuits and are bonded to the first bonding pads. The cell array structure may include a lower layer including a first region and a second region, the lower layer extending in a first direction and a second direction perpendicular to the first direction, a stack including word lines and interlayer insulating patterns, which are alternately stacked in a third direction perpendicular to the first direction and the second direction, each of the word lines having a word line pad in the second region, and the stack having a staircase structure in the second region, bit lines extending along the third direction to cross the word lines, and cell contact plugs provided on the second region and respectively coupled to the word line pads, the cell contact plugs connected to the first bonding pads. According to an embodiment of the inventive concept, a method of fabricating a semiconductor memory device may include forming a first mold structure including first and second semiconductor layers, which are alternatingly stacked on a substrate including first and second regions, replacing the first mold structure in the firs