US-12628333-B2 - Semiconductor device including a seperation layer

Abstract

A semiconductor device includes an active region defined by a device isolation layer, a pad layer on the device isolation layer and a first region of the active region, a first separation layer penetrating through the pad layer and extending in a first direction, a second separation layer penetrating through the pad layer and extending in a second direction, a word line below the second separation layer, extending in the second direction, and embedded in a substrate, a bit line extending in the first direction and connected to a second region of the active region, a contact structure on a side surface of the bit line and connected to the pad layer, and an data storage structure on the contact structure and connected to the contact structure. The first separation layer includes an airgap or a material having a dielectric constant less than a dielectric constant of silicon nitride.

Inventors

• JUNHYEOK AHN

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20230531

Priority Date

20220712

Claims (20)

1. 1 . A semiconductor device comprising: an active region defined by a device isolation layer in a substrate; a pad layer on the device isolation layer and a first region of the active region; a first separation layer penetrating through the pad layer and extending in a first direction; a second separation layer penetrating through the pad layer and extending in a second direction, intersecting the first direction; a word line buried in the substrate and disposed below the second separation layer, wherein the word line extends across the active region in the second direction; a bit line extending in the first direction on the first separation layer and connected to a second region of the active region; a contact structure on a side surface of the bit line and connected to a portion of the pad layer; and a data storage structure on the contact structure and electrically connected to the contact structure, wherein the first separation layer includes at least one of an air gap and a material having a dielectric constant less than a dielectric constant of silicon nitride.
2. 2 . The semiconductor device of claim 1 , wherein a lower surface of the first separation layer is located at a level lower than a level of a lower surface of the pad layer.
3. 3 . The semiconductor device of claim 1 , wherein the first separation layer includes an air gap, wherein the first separation layer further includes an insulating pattern on the air gap, and wherein the air gap is an empty space surrounded by the second separation layer, the insulating pattern, and at least one of the active region and the device isolation layer.
4. 4 . The semiconductor device of claim 3 , wherein the pad layer includes polysilicon, and wherein the insulating pattern includes silicon nitride.
5. 5 . The semiconductor device of claim 1 , further comprising: a bit line contact hole exposing the second region of the active region; and a bit line contact spacer disposed in the bit line contact hole, wherein the bit line includes a first conductive pattern, wherein the first conductive pattern includes a bit line contact pattern disposed in the bit line contact hole and contacting the second region of the active region exposed by the bit line contact hole, wherein the bit line contact spacer covers a side surface of the bit line contact pattern, and wherein a lower end of the bit line contact pattern is at a level lower than a level of a lower end of the bit line contact spacer.
6. 6 . The semiconductor device of claim 1 , wherein the pad layer includes a pad protrusion contacting a protruding upper side surface of the active region protruding from an upper surface of the device isolation layer, and wherein the first separation layer contacts the pad protrusion.
7. 7 . A semiconductor device comprising: an active region defined by a device isolation layer in a substrate; a pad layer on the device isolation layer and a first region of the active region; a first separation layer penetrating through the pad layer and extending in a first direction; a bit line extending on the substrate in the first direction and connected to a second region of the active region; and a contact structure on a side surface of the bit line and connected to a portion of the pad layer, wherein the first separation layer includes an air gap and an insulating pattern on the air gap.
8. 8 . The semiconductor device of claim 7 , wherein the air gap is an empty space surrounded by the insulating pattern and at least one of the active region and the device isolation layer.
9. 9 . The semiconductor device of claim 7 , wherein the device isolation layer has a recessed upper surface, and wherein the air gap is disposed between the insulating pattern and the recessed upper surface of the device isolation layer.
10. 10 . The semiconductor device of claim 7 , wherein the air gap is disposed between the insulating pattern and each of the active region and the device isolation layer.
11. 11 . The semiconductor device of claim 7 , wherein the insulating pattern includes a first insulating layer and a second insulating layer on the first insulating layer, and wherein the first insulating layer surrounds a lower surface and side surfaces of the second insulating layer.
12. 12 . The semiconductor device of claim 7 , further comprising: a bit line contact hole exposing the second region of the active region, wherein the bit line includes a first conductive pattern, and wherein the first conductive pattern includes a bit line contact pattern disposed in the bit line contact hole and contacting the second region of the active region exposed by the bit line contact hole.
13. 13 . The semiconductor device of claim 12 , wherein a lower surface of the bit line contact pattern includes a first portion and a second portion around the first portion, and wherein the first portion convexly protrudes downwards from the second portion.
14. 14 . The semiconductor device of claim 13 , further comprising: a bit line contact spacer disposed in the bit line contact hole and covering a side surface of the bit line contact pattern, wherein the first portion of the bit line contact pattern is positioned at a level lower than a level of a lower end of the bit line contact spacer.
15. 15 . The semiconductor device of claim 7 , further comprising: a second separation layer penetrating through the pad layer and extending in a second direction, intersecting the first direction.
16. 16 . The semiconductor device of claim 15 , further comprising: a word line disposed below the second separation layer, wherein the word line extends across the active region and extends into the device isolation layer.
17. 17 . A semiconductor device comprising: an active region defined by a device isolation layer in a substrate; a pad layer on the device isolation layer and a first region of the active region; a separation layer penetrating through the pad layer and extending in a first direction, wherein the separation layer contacts the device isolation layer at a level below a top surface of the active region; a bit line extending on the substrate in the first direction and connected to a second region of the active region; and a contact structure on a side surface of the bit line and connected to a portion of the pad layer, wherein the separation layer has a dielectric constant less than a dielectric constant of silicon nitride.
18. 18 . The semiconductor device of claim 17 , wherein the separation layer includes at least one of silicon oxide, silicon oxycarbide, and silicon oxycarbonitride.
19. 19 . The semiconductor device of claim 17 , wherein the separation layer includes an air gap having a dielectric constant less than a dielectric constant of silicon nitride and an insulating pattern on the air gap, wherein the pad layer includes a pad protrusion contacting the device isolation layer, and wherein a lower end of the pad protrusion is located at a level lower than a level of an upper end of the active region and is located at a level higher than a level of a lower end of the air gap.
20. 20 . The semiconductor device of claim 17 , wherein the separation layer includes: an insulating layer comprising at least one of silicon oxide, silicon oxycarbide, and silicon oxycarbonitride; and a capping layer disposed on the insulating layer and comprising silicon nitride.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application claims the benefit under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0085548 filed on Jul. 12, 2022 in the Korean Intellectual Property Office, the disclosure of which is herein incorporated by reference in its entirety. BACKGROUND 1. Field The present inventive concept relates to a semiconductor device. 2. Description of Related Art According to the development of the electronics industry and the needs of users, electronic devices are becoming smaller in size and higher in performance. Accordingly, semiconductor devices used in electronic devices are also required to be highly integrated and high-performance. In order to fabricate a highly scaled semiconductor device, a technique for forming separation layers that electrically separating pad layers from each other on active regions is desirable. SUMMARY Example embodiments provide a semiconductor device having improved electrical characteristics and reliability. According to example embodiments, a semiconductor device includes an active region defined by a device isolation layer in a substrate; a pad layer on the device isolation layer and a first region of the active region; a first separation layer penetrating through the pad layer and extending in a first direction; a second separation layer penetrating through the pad layer and extending in a second direction, intersecting the first direction; a word line buried in the substrate and disposed below the second separation layer, the word line extending across the active region in the second direction; a bit line extending in the first direction on the first separation layer and connected to a second region of the active region; a contact structure on a side surface of the bit line and connected to a portion of the pad layer; and a data storage structure on the contact structure and electrically connected to the contact structure. The first separation layer includes at least one of an airgap and a material having a dielectric constant less than a dielectric constant of silicon nitride. According to example embodiments, a semiconductor device includes an active region defined by a device isolation layer in a substrate; a pad layer on the device isolation layer and a first region of the active region; a first separation layer penetrating through the pad layer and extending in a first direction; a bit line extending on the substrate in the first direction and connected to a second region of the active region; and a contact structure on a side surface of the bit line and connected to a portion of the pad layer. The first separation layer includes an airgap and an insulating pattern on the airgap. According to example embodiments, a semiconductor device includes an active region defined by a device isolation layer in a substrate; a pad layer on the device isolation layer and a first region of the active region; a separation layer penetrating through the pad layer and extending in a first direction; a bit line extending on the substrate in the first direction and connected to a second region of the active region; and a contact structure on a side surface of the bit line and connected to a portion of the pad layer. The separation layer has a material having a dielectric constant less than a dielectric constant of silicon nitride. BRIEF DESCRIPTION OF DRAWINGS The above and other aspects, features, and advantages of the present inventive concept will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which: FIG. 1 is a plan view of a semiconductor device according to example embodiments; FIG. 2 is a cross-sectional view of a semiconductor device according to example embodiments; FIGS. 3A to 3F are partially enlarged cross-sectional views of semiconductor devices according to example embodiments; FIGS. 4A and 4B are partially enlarged cross-sectional views of semiconductor devices according to example embodiments; FIGS. 5A to 5I are cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments; FIGS. 6A to 6G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments; and FIGS. 7A and 7B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION Hereinafter, example embodiments will be described with reference to the accompanying drawings. FIG. 1 is a plan view of a semiconductor device according to example embodiments. FIG. 2 is a cross-sectional view of a semiconductor device according to example embodiments. FIG. 2 illustrates cross-sections of the semiconductor device of FIG. 1 taken along lines I-I′ and FIG. 3A is a partially enlarged cross-sectional view of a semiconductor device according to example embodiments. FIG. 3A is an enlarged view of area ‘A’ of FIG. 2. Referr