US-12628335-B2 - Support layer for small pitch fill

US12628335B2US 12628335 B2US12628335 B2US 12628335B2US-12628335-B2

Abstract

Provided is a DRAM device having a support layer to hold the bWL features before being filled with the electrode metal. The support layer keeps the structure supported from the top surface but does not prevent the gap fill. A temporary gap-fill material is first deposited in the bWL gaps and then recessed to expose the top edges. A support layer material is then deposited on the structure by plasma enhanced chemical vapor deposition (PECVD). The device is then patterned orthogonal and with pitch greater than the bWL pitch. The temporary gap-fill material is then removed, forming support beams comprising the support material. A metal can then be deposited to fill the bWL gaps under the support beams.

Inventors

Fredrick Fishburn
Sung-Kwan Kang

Assignees

APPLIED MATERIALS, INC.

Dates

Publication Date: 20260512
Application Date: 20230316

Claims (14)

1 . A memory device comprising: a substrate with a substrate surface having a plurality of trenches extending a depth into the substrate, each of the plurality of trenches including a top portion, a bottom portion with a bottom surface, and a sidewall surface; a gate oxide layer on the top portion, the bottom portion, the bottom surface, and the sidewall surface of each of the plurality of trenches; a gapfill material on the gate oxide layer and in each of the plurality of trenches; and a beam extending on a top surface of the gate oxide layer and between the plurality of trenches in the top portion of each of the plurality of trenches, the beam comprising a support layer.
2 . The memory device of claim 1 , wherein the support layer comprises one or more of poly-silicon, a low temperature oxide, a high-K material, a metal, a metal nitride, and p-doped poly-silicon.
3 . The memory device of claim 1 , wherein the gate oxide layer comprises one or more of an oxide, a low-K dielectric material, a high-K dielectric material, and an annealed oxide material.
4 . The memory device of claim 3 , wherein the gate oxide layer has a thickness in a range of from 5 nm to 7 nm.
5 . The memory device of claim 1 , wherein the recessed gapfill material comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), molybdenum (Mo), and tungsten (W).
6 . The memory device of claim 1 , wherein the plurality of trenches has an aspect ratio greater than or equal to 10:1.
7 . A memory device comprising: a plurality of buried worldline gate stacks on a semiconductor substrate, each of the plurality of buried wordline gate stacks comprising an active region, a nitride layer, and a pad oxide; a plurality of trenches adjacent to the plurality of buried wordline gate stacks, the plurality of trenches extending a depth from a top surface of the nitride layer into the semiconductor substrate, each of the plurality of trenches including a top portion, a bottom portion with a bottom surface, and a sidewall surface; a gate oxide layer on the plurality of buried wordline gate stacks and on the bottom surface and the sidewall surface of the plurality of trenches; a gapfill material on the gate oxide layer and in each of the plurality of trenches; and a beam on a top surface of the plurality of buried wordline gate stacks and between the plurality of trenches in the top portion of the plurality of trenches, the beam comprising a support layer.
8 . The memory device of claim 7 , wherein the support layer comprises one or more of poly-silicon, a low temperature oxide, a high-K material, a metal, a metal nitride, and p-doped poly-silicon.
9 . The memory device of claim 7 , wherein the gate oxide layer comprises one or more of an oxide, a low-K dielectric material, a high-K dielectric material, and an annealed oxide material.
10 . The memory device of claim 7 , wherein the gate oxide layer has a thickness in a range of from 5 nm to 7 nm.
11 . The memory device of claim 7 , wherein the gapfill material comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), molybdenum (Mo), and tungsten (W).
12 . The memory device of claim 7 , wherein the plurality of trenches have an aspect ratio greater than or equal to 10:1.
13 . The memory device of claim 7 , wherein a recess in each of the plurality of trenches has a depth in a range of from greater than 0 nm to 15 nm.
14 . The memory device of claim 1 , wherein the memory device is a DRAM device.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Application No. 63/322,732, filed Mar. 23, 2022, the entire disclosure of which is hereby incorporated by reference herein. TECHNICAL FIELD Embodiments of the present disclosure pertain to the field of electronic devices and electronic device manufacturing. More particularly, embodiments of the disclosure provide electronic devices including a support layer to hold buried wordline features before filled and methods of forming same. BACKGROUND Electronic devices, such as personal computers, workstations, computer servers, mainframes, and other computer related equipment such as printers, scanners and hard disk drives use memory devices that provide substantial data storage capability, while incurring low power consumption. There are two major types of random-access memory cells, dynamic and static, which are well-suited for use in electronic devices. Dynamic random-access memories (DRAMs) can be programmed to store a voltage which represents one of two binary values but require periodic reprogramming or “refreshing” to maintain this voltage for more than very short periods of time. Static random-access memories (SRAM) are so named because they do not require periodic refreshing. DRAM memory circuits are manufactured by replicating billions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor. The manufacturing of a DRAM cell includes the fabrication of a transistor, a capacitor, and three contacts: one each to the bit line, the word line, and the reference voltage. DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and to increase memory cell density to allow more memory to be squeezed onto a single memory chip, especially for densities greater than 8 Gigabits. Limitations on cell size reduction include the passage of both active and passive word lines through the cell, the size of the cell capacitor, and the compatibility of array devices with non-array devices. One difficulty with DRAM is that the buried wordline needs to be a low resistance metal which can withstand high temperatures. Soon the buried wordline pitch will be 30 nm or less, and further generations continue to shrink. The mechanical stability of the buried wordline is already challenged and getting worse. Current methods use lower stress films or “V” shape gaps, but these methods result in higher resistance. Even with this there is bending, and any imbalance in the gap to be filled results in worse bending of the lines. This bending not only results in imbalance in the width of the gap that is filled with metal but also causes misalignment locally in the line between gaps. In the case of buried wordline, this is misalignment of the silicon which forms the cell and bitline contact regions. Thus, there is a need in the art for improved DRAM and methods of manufacture. SUMMARY One or more embodiments of the disclosure are directed to a memory device. In one or more embodiments, the memory comprises: a substrate with a substrate surface having a plurality of trenches extending a depth into the substrate, each trench including a bottom and sidewall; and a beam extending on the substrate surface between the plurality of trenches, the beam comprising a support layer. Additional embodiments of the disclosure are directed to a method of forming a memory device. In one or more embodiments, the method comprises: providing a substrate having plurality of trenches thereon; depositing a temporary fill layer on a top surface of the substrate to seal the plurality of trenches; recessing the temporary fill layer to form a recess in each of the plurality of trenches; depositing a support layer material in the recess; removing the temporary fill material to expose a sidewall and a bottom surface of each of the plurality of trenches; depositing a gapfill material in the plurality of trenches; and removing the support layer material. BRIEF DESCRIPTION OF THE DRAWINGS So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments. The embodiments as described herein are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements. FIG