US-12628337-B2 - Semiconductor memory device

Abstract

A semiconductor memory device may include a substrate including a cell array region and a peripheral circuit region, an active pattern on the cell array region of the substrate, a peripheral active pattern on the peripheral circuit region of the substrate, a peripheral gate electrode disposed on a top surface of the peripheral active pattern, a first interlayer insulating pattern provided on the cell array region to cover a top surface of the active pattern, a first etch stop layer covering the first interlayer insulating pattern and the peripheral gate electrode with a uniform thickness, and a second interlayer insulating pattern disposed on the first etch stop layer and in the peripheral circuit region. In the cell array region, the second interlayer insulating pattern may have a top surface, which is located at substantially the same level as a top surface of the first etch stop layer.

Inventors

• Taegyu Kang
• Taehyuk Kim
• Seok-ho Shin
• Keunnam Kim
• Seokhan Park
• Joongchan SHIN
• Kiseok LEE

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20230906

Priority Date

20221028

Claims (20)

1. 1 . A semiconductor memory device, comprising: a substrate including a cell array region and a peripheral circuit region; an active pattern on the cell array region of the substrate; a peripheral active pattern on the peripheral circuit region of the substrate; a peripheral gate electrode disposed on a top surface of the peripheral active pattern; a first interlayer insulating pattern provided on the cell array region to cover a top surface of the active pattern; a first etch stop layer covering the first interlayer insulating pattern and the peripheral gate electrode with a uniform thickness; and a second interlayer insulating pattern disposed on the first etch stop layer and in the peripheral circuit region, wherein, in the cell array region, the second interlayer insulating pattern has a top surface that is located at substantially the same level as a top surface of the first etch stop layer.
2. 2 . The semiconductor memory device as claimed in claim 1 , further including: a contact pattern that is provided in the cell array region to penetrate the first etch stop layer and the first interlayer insulating pattern and to be in contact with the top surface of the active pattern; and a peripheral contact plug, which is provided in the peripheral circuit region to penetrate the second interlayer insulating pattern and the first etch stop layer and to be in contact with the top surface of the peripheral active pattern.
3. 3 . The semiconductor memory device as claimed in claim 2 , further comprising a data storage pattern disposed on the contact pattern.
4. 4 . The semiconductor memory device as claimed in claim 1 , further including a second etch stop layer, which is disposed between the first interlayer insulating pattern and the top surface of the active pattern in the cell array region and between the first etch stop layer and the top surface of the peripheral active pattern in the peripheral circuit region.
5. 5 . The semiconductor memory device as claimed in claim 4 , wherein the first etch stop layer is in contact with a top surface of the second etch stop layer in the peripheral circuit region.
6. 6 . The semiconductor memory device as claimed in claim 1 , further including a third etch stop layer, which is disposed in the cell array region to cover the top surface of the first etch stop layer and is disposed in the peripheral circuit region to cover the top surface of the second interlayer insulating pattern.
7. 7 . The semiconductor memory device as claimed in claim 1 , wherein: the top surface of the peripheral active pattern is substantially coplanar with the top surface of the active pattern, and a bottom surface of the peripheral active pattern is substantially coplanar with a bottom surface of the active pattern.
8. 8 . The semiconductor memory device as claimed in claim 1 , further including: a bit line, which is in contact with a bottom surface of the active pattern and is extended in a first direction; a word line, which is adjacent to a first side surface of the active pattern and is extended in a second direction crossing the first direction; and a back-gate electrode, which is adjacent to a second side surface of the active pattern and is extended in the second direction.
9. 9 . The semiconductor memory device as claimed in claim 8 , wherein a top surface of the word line and a top surface of the back-gate electrode are located at a level lower than the top surface of the active pattern.
10. 10 . The semiconductor memory device as claimed in claim 8 , further including: a spacer insulating layer conformally covering the bit line; and a shielding conductive pattern on the spacer insulating layer, the shielding conductive pattern including a line portion extended parallel to the bit line and in the first direction.
11. 11 . The semiconductor memory device as claimed in claim 8 , further including: a spacer insulating layer conformally covering the bit line; and peripheral circuit patterns disposed on a bottom surface of the peripheral active pattern, wherein the spacer insulating layer conformally covers the peripheral circuit patterns, in the peripheral circuit region.
12. 12 . A semiconductor memory device, comprising: a substrate including a cell array region and a peripheral circuit region; a bit line extended from the cell array region in a first direction; a first active pattern and a second active pattern disposed on the bit line; a back-gate electrode disposed between the first and second active patterns and extending in a second direction to cross the bit line; a first word line disposed adjacent to a first side surface of the first active pattern and extending in the second direction; a second word line disposed adjacent to a second side surface of the second active pattern and extending in the second direction; a peripheral active pattern on the peripheral circuit region of the substrate; a peripheral gate electrode on the peripheral active pattern; a first interlayer insulating pattern disposed in the cell array region to cover top surfaces of the first active pattern and the second active pattern; a first etch stop layer covering the first interlayer insulating pattern and the peripheral gate electrode with a uniform thickness; a second etch stop layer disposed between the first interlayer insulating pattern and the top surfaces of the first active pattern and the second active pattern in the cell array region and between the first etch stop layer and a top surface of the peripheral active pattern and the peripheral gate electrode in the peripheral circuit region; and a second interlayer insulating pattern disposed on the first etch stop layer in the peripheral circuit region.
13. 13 . The semiconductor memory device as claimed in claim 12 , wherein: the top surface of the peripheral active pattern is substantially coplanar with the top surfaces of the first and second active patterns, and a bottom surface of the peripheral active pattern is substantially coplanar with bottom surfaces of the first and second active patterns.
14. 14 . The semiconductor memory device as claimed in claim 13 , further including peripheral circuit patterns disposed on the bottom surface of the peripheral active pattern.
15. 15 . The semiconductor memory device as claimed in claim 12 , wherein a top surface of the second interlayer insulating pattern is substantially coplanar with a top surface of the first etch stop layer in the cell array region.
16. 16 . The semiconductor memory device as claimed in claim 12 , further including: contact patterns, which are provided in the cell array region to penetrate the first etch stop layer, the first interlayer insulating pattern, and the second etch stop layer and are coupled to the first and second active patterns, respectively; and a peripheral contact plug, which is provided in the peripheral circuit region to penetrate the second interlayer insulating pattern, the first etch stop layer, and the second etch stop layer to be in contact with the top surface of the peripheral active pattern.
17. 17 . The semiconductor memory device as claimed in claim 12 , wherein top surfaces of the first and second word lines and a top surface of the back-gate electrode are located at a level lower than the top surfaces of the first and second active patterns.
18. 18 . A semiconductor memory device, comprising: a substrate including a cell array region and a peripheral circuit region; bit lines provided on the cell array region of the substrate and extending in a first direction; a shielding conductive pattern including line portions, which are respectively disposed between adjacent ones of the bit lines and extend in the first direction; first active patterns and second active patterns alternately disposed in the first direction on each of the bit lines; back-gate electrodes, which are respectively disposed between the first active patterns and the second active patterns that are adjacent to each other in the first direction, and which extend in a second direction to cross the bit lines; first word lines, which are respectively disposed adjacent to first side surfaces of the first active patterns and extend in the second direction; second word lines, which are respectively disposed adjacent to second side surfaces of the second active patterns and extend in the second direction; a first interlayer insulating pattern disposed in the cell array region to cover top surfaces of the first active patterns and the second active patterns; a peripheral active pattern on the peripheral circuit region of the substrate; a peripheral gate electrode on the peripheral active pattern; a first etch stop layer covering the first interlayer insulating pattern and the peripheral gate electrode with a uniform thickness; a second interlayer insulating pattern disposed on the first etch stop layer and in the peripheral circuit region; a second etch stop layer, which is disposed between the first interlayer insulating pattern and the top surfaces of the first active patterns and the second active patterns in the cell array region and is disposed between the first etch stop layer and a top surface of the peripheral active pattern in the peripheral circuit region; contact patterns, which are disposed in the cell array region to penetrate the first etch stop layer, the first interlayer insulating pattern, and the second etch stop layer and are respectively coupled to the first and second active patterns; a peripheral contact plug, which is disposed in the peripheral circuit region to penetrate the second interlayer insulating pattern, the first etch stop layer, and the second etch stop layer and is in contact with the top surface of the peripheral active pattern; and data storage patterns coupled to the contact patterns, respectively.
19. 19 . The semiconductor memory device as claimed in claim 18 , further including: a first back-gate capping pattern between the contact patterns and the back-gate electrodes; first gate capping patterns between the contact patterns and the first and second word lines; a second back-gate capping pattern between the bit lines and the back-gate electrodes; and second gate capping patterns between the bit lines and the first and second word lines.
20. 20 . The semiconductor memory device as claimed in claim 18 , further including: a spacer insulating layer conformally covering the bit lines; and peripheral circuit patterns disposed on a bottom surface of the peripheral active pattern, wherein the spacer insulating layer conformally covers the peripheral circuit patterns, in the peripheral circuit region.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0140981, filed on Oct. 28, 2022, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference. BACKGROUND 1. Field The present disclosure relates to a semiconductor memory device. 2. Description of the Related Art Higher integration of semiconductor devices is desired to satisfy consumer demands for superior performance and inexpensive prices. In the case of semiconductor devices, since a degree of integration is an important factor in determining product prices, increased integration is especially desirable. In the case of two-dimensional or planar semiconductor devices, their degree of integration is mainly determined by the area occupied by a unit memory cell. Integration may be greatly influenced by the level of fine patter-forming technology. However, the extremely expensive process equipment needed to increase pattern fineness sets a practical limitation on the ability to increase integration for two-dimensional or planar semiconductor devices. Accordingly, various semiconductor technologies have been suggested to improve integration density, resistance, and current driving ability of a semiconductor device. SUMMARY According to an embodiment, a semiconductor memory device may include a substrate including a cell array region and a peripheral circuit region, an active pattern on the cell array region of the substrate, a peripheral active pattern on a peripheral circuit region of the substrate, a peripheral gate electrode disposed on a top surface of the peripheral active pattern, a first interlayer insulating pattern provided on the cell array region to cover a top surface of the active pattern, a first etch stop layer covering the first interlayer insulating pattern and the peripheral gate electrode with a uniform thickness, and a second interlayer insulating pattern on the first etch stop layer and in the peripheral circuit region. In the cell array region, the second interlayer insulating pattern may have a top surface that is located at substantially the same level as a top surface of the first etch stop layer. According to an embodiment, a semiconductor memory device may include a substrate including a cell array region and a peripheral circuit region, a bit line that extends from the cell array region in a first direction, a first active pattern and a second active pattern disposed on the bit line, a back-gate electrode disposed between the first and second active patterns and that extend in a second direction to cross the bit line, a first word line disposed adjacent to a first side surface of the first active pattern and extending in the second direction, a second word line disposed adjacent to a second side surface of the second active pattern and extending in the second direction, a peripheral active pattern on the peripheral circuit region of the substrate, a peripheral gate electrode on the peripheral active pattern, a first interlayer insulating pattern disposed in the cell array region to cover a top surface of the active pattern, a first etch stop layer covering the first interlayer insulating pattern and the peripheral gate electrode with a uniform thickness, a second etch stop layer disposed between the first interlayer insulating pattern and the top surface of the active pattern in in the cell array region and between the first etch stop layer and a top surface of the peripheral active pattern and the peripheral gate electrode in the peripheral circuit region, and a second interlayer insulating pattern disposed on the first etch stop layer in the peripheral circuit region. According to an embodiment, a semiconductor memory device may include a substrate including a cell array region and a peripheral circuit region, bit lines provided on the cell array region of the substrate and extending in a first direction, a shielding conductive pattern including line portions, which are respectively disposed between adjacent ones of the bit lines and which extend in the first direction. First and second active patterns may be alternately disposed in the first direction on each of the bit lines, back-gate electrodes, which are respectively disposed between the first and second active patterns that are adjacent to each other in the first direction, and which extend in the second direction to cross the bit lines, first word lines, which are respectively disposed adjacent to first side surfaces of the first active patterns and extend in the second direction, second word lines, which are respectively disposed adjacent to second side surfaces of the second active patterns and extend in the second direction, a first interlayer insulating pattern disposed in the cell array region to cover a top surface of the active pattern, a peripheral active pattern on the peripheral circuit region of the su