US-12628338-B2 - Semiconductor device

Abstract

A semiconductor device including a substrate including a cell array region and a peripheral circuit region, the substrate including first active region defined in the cell array region and second active region defined in the peripheral circuit region, a plurality of word lines in the substrate and extending in a first direction, a bit line in the cell array region and extending in a second direction perpendicular to the first direction, a plurality of first pad separation patterns on corresponding once of the word lines, respectively, and extending in the first direction, a cell pad structure on the substrate and between two adjacent ones of the first pad separation patterns, and a second pad separation pattern between two adjacent ones of the first pad separation patterns and being adjacent to the cell pad structure may be provided.

Inventors

• Eunjung KIM
• Jaehyung Park
• Kihyung NAM
• Hoju Song
• Yunjae Lee

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20230629

Priority Date

20220720

Claims (20)

1. 1 . A semiconductor device comprising: a substrate including a cell array region and a peripheral circuit region, the substrate including a plurality of first active regions defined in the cell array region and at least one second active region defined in the peripheral circuit region; a plurality of word lines in the substrate and extending in a first direction; a plurality of bit lines in the cell array region of the substrate and extending in a second direction perpendicular to the first direction; a plurality of first pad separation patterns on corresponding ones of the word lines, respectively, the first pad separation patterns extending in the first direction; a cell pad structure on the substrate and between two adjacent ones of the first pad separation patterns; and a second pad separation pattern between two adjacent ones of the first pad separation patterns and being adjacent to the cell pad structure, wherein a cross-section of the cell pad structure perpendicular to the first direction has a quadrangular shape, in which both corners of a lower surface of the cross-section are rounded, and upper surfaces of the plurality of first pad separation patterns, the cell pad structure, and the second pad separation pattern are on a same plane.
2. 2 . The semiconductor device of claim 1 , wherein a cross-section of the cell pad structure perpendicular to the second direction includes a first corner and a second corner at a lower surface thereof, the first corner adjacent to the second pad separation pattern and having a rounded shape, the second corner having a square shape.
3. 3 . The semiconductor device of claim 1 , wherein a cross-section of the cell pad structure perpendicular to the second direction has a quadrangular shape, in which two opposite corners of a lower surface of the cross-section are angled.
4. 4 . The semiconductor device of claim 1 , wherein an upper surface of each of the first active regions is at a lower vertical level than an upper surface of the second active region.
5. 5 . The semiconductor device of claim 1 , wherein an upper surface of the cell pad structure is at a higher vertical level than an upper surface of the second active region, and a lower surface of the cell pad structure is at a lower vertical level than the upper surface of the second active region.
6. 6 . The semiconductor device of claim 1 , wherein an upper surface of the cell pad structure is at a same vertical level as an upper surface of the second active region, and a lower surface of the cell pad structure is at a lower vertical level than the upper surface of the second active region.
7. 7 . The semiconductor device of claim 1 , further comprising: a capping insulating film between a corresponding one of the word lines and a corresponding one of the first pad separation patterns, wherein a length in the second direction of the corresponding one of the first pad separation patterns is same as a length in the second direction of the capping insulating film.
8. 8 . The semiconductor device of claim 7 , wherein the capping insulating film and the corresponding one of the first pad separation patterns are portions of a single integral structure, respectively.
9. 9 . The semiconductor device of claim 1 , wherein an upper surface of the cell pad structure is at a same vertical level as an upper surface of the second pad separation pattern, and the lower surface of the cell pad structure is at a higher vertical level than a lower surface of the second pad separation pattern.
10. 10 . A semiconductor device comprising: a substrate including a cell array region, a boundary region, and a peripheral circuit region, the substrate including a plurality of first active regions defined in the cell array region and at least one second active region defined in the peripheral circuit region; a word line in the substrate and extending in a first direction; a bit line in the cell array region of the substrate and extending in a second direction perpendicular to the first direction; a plurality of first pad separation patterns on the word line, the first pad separation patterns extending in the first direction; a cell pad structure on the substrate and between two adjacent ones of the first pad separation patterns; a second pad separation pattern between two adjacent ones of the first pad separation patterns, and the second pad separation pattern being adjacent to the cell pad structure; a first insulating layer on the cell pad structure and extending to the boundary region; and a second insulating layer on the first insulating layer and extending to the boundary region, wherein a first cross-section of the cell pad structure perpendicular to the first direction has a quadrangular shape, in which both corners of a lower surface are rounded, and wherein an upper surface of the first insulating layer and an upper surface of the second insulating layer are flat, and upper surfaces of the plurality of first pad separation patterns, the cell pad structure, and the second pad separation pattern are on a same plane.
11. 11 . The semiconductor device of claim 10 , wherein a second cross-section of the cell pad structure perpendicular to the second direction includes a first corner and a second corner at a lower surface thereof, the first corner being adjacent to the second pad separation pattern and having rounded corner, the second corner having a square shape.
12. 12 . The semiconductor device of claim 10 , wherein a second cross-section of the cell pad structure perpendicular to the second direction has a quadrangular shape, in which both corners of a lower surface are angled.
13. 13 . The semiconductor device of claim 10 , wherein an upper surface of the cell pad structure is at a higher vertical level than an upper surface of the second active region, and a lower surface of the cell pad structure is at a lower vertical level than the upper surface of the second active region.
14. 14 . The semiconductor device of claim 10 , wherein an upper surface of the cell pad structure is at same vertical level as an upper surface of the second active region, and a lower surface of the cell pad structure is at a lower vertical level than the upper surface of the second active region.
15. 15 . The semiconductor device of claim 10 , further comprising: a capping insulating film in a word line trench extending into the substrate, the capping insulating film being between the word line and a corresponding one of the first pad separation patterns, wherein the corresponding one of the first pad separation patterns is aligned with the capping insulating film in a third direction, the third direction being perpendicular to both the first direction and the second direction.
16. 16 . The semiconductor device of claim 15 , wherein the capping insulating film and the corresponding one of the first pad separation patterns are portions of a single integral structure, respectively.
17. 17 . A semiconductor device comprising: a substrate including a cell array region, a boundary region, and a peripheral circuit region, the substrate including a plurality of first active regions defined in the cell array region and at least one second active region defined in the peripheral circuit region; a word line in the substrate and extending in a first direction; a capping insulating film on the word line; a bit line in the cell array region of the substrate and extending in a second direction perpendicular to the first direction; a direct contact between the bit line and a corresponding one of the first active regions; a plurality of cell pad structures in contact with the first active regions, respectively, the cell pad structures being on the substrate; a buried contact on a corresponding one of the cell pad structures; a first pad separation pattern on the word line and extending in the first direction; a second pad separation pattern between two adjacent ones of the cell pad structures and extending in the second direction; a buffer layer on the cell pad structures and extending to the boundary region; and a first insulating layer on the buffer layer and extending to the boundary region, wherein a first cross-section of each of the cell pad structures perpendicular to the first direction has a quadrangular shape, in which both corners of a lower surface are rounded, wherein an upper surface of the buffer layer and an upper surface of the first insulating layer are flat, wherein the capping insulating film and the first pad separation pattern are portions of a single integral structure, respectively, and wherein upper surfaces of the first pad separation pattern, the cell pad structures, and the second pad separation pattern are on a same plane.
18. 18 . The semiconductor device of claim 17 , wherein a second cross-section of each of the cell pad structures perpendicular to the second direction includes a first corner and a second corner at a lower surface thereof, the first corner being adjacent to the second pad separation pattern and having a rounded corner, the second corner having a square shape.
19. 19 . The semiconductor device of claim 17 , wherein a second cross-section of each of the cell pad structures perpendicular to the second direction has a quadrangular shape, in which both corners of a lower surface of the cross-section are angled.
20. 20 . The semiconductor device of claim 17 , wherein an upper surface of each of the cell pad structures is at a higher vertical level than an upper surface of the second active region, and a lower surface of each of the cell pad structures is at a lower vertical level than the upper surface of the second active region.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0089883, filed on Jul. 20, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND The inventive concepts relate to semiconductor devices. More particularly, the inventive concepts relate to semiconductor devices including a cell pad structure. With the development of the electronics industry, semiconductor devices are gradually being downscaled. Accordingly, the size of individual microcircuit patterns for implementing a semiconductor device is further reduced. In addition, as the integrated circuit device is highly integrated, the line width of the bit line decreases and the difficulty of the process for forming the contact between the bit lines increases. SUMMARY The inventive concepts provide semiconductor devices capable of reducing the cost of a semiconductor device manufacturing process while improving reliability. According to an aspect of the inventive concepts, a semiconductor device including a substrate includes a cell array region and a peripheral circuit region, the substrate including a plurality of first active regions defined in the cell array region and at least one second active region defined in the peripheral circuit region, a plurality of word lines in the substrate and extending in a first direction, a plurality of bit lines in the cell array region of the substrate and extending in a second direction perpendicular to the first direction, a plurality of first pad separation patterns on corresponding ones of the word lines, respectively, the first pad separation patterns extending in the first direction, a cell pad structure on the substrate and being between two adjacent ones of the first pad separation patterns, and a second pad separation pattern between two adjacent ones of the first pad separation patterns and being adjacent to the cell pad structure, wherein a cross-section of the cell pad structure perpendicular to the first direction has a quadrangular shape in which both corners of a lower surface are rounded. According to another aspect of the inventive concepts, a semiconductor device including a substrate includes a cell array region, a boundary region, and a peripheral circuit region, the substrate including a plurality of first active regions defined in the cell array region and at least one second active region defined in the peripheral circuit region, a word line in the substrate and extending in a first direction, a bit line in the cell array region of the substrate and extending in a second direction perpendicular to the first direction, a plurality of first pad separation patterns on the word line, the first pad separation patterns extending in the first direction, a cell pad structure on the substrate and between two adjacent ones of the first pad separation patterns, a second pad separation pattern between two adjacent ones of the first pad separation patterns the second pad separation pattern being adjacent to the cell pad structure, a first insulating layer on the cell pad structure and extending to the boundary region, and a second insulating layer on the first insulating layer and extending to the boundary region, wherein a first cross-section of the cell pad structure perpendicular to the first direction has a quadrangular shape, in which both corners of a lower surface are rounded, and wherein an upper surface of the first insulating layer and an upper surface of the second insulating layer are flat. According to another aspect of the inventive concepts, a semiconductor device includes a substrate including a cell array region, a boundary region, and a peripheral circuit region, the substrate including a plurality of first active regions defined in the cell array region and at least one second active region defined in the peripheral circuit region, a word line in the substrate and extending in a first direction, a capping insulating film on the word line, a bit line in the cell array region of the substrate and extending in a second direction perpendicular to the first direction, a direct contact between the bit line and a corresponding one of the first active regions, a plurality of cell pad structures in contact with the first active regions, respectively, the cell pad structures being on the substrate, a buried contact on a corresponding one of the cell pad structures, a first pad separation pattern on the word line and extending in the first direction, a second pad separation pattern between two adjacent ones of the cell pad structures and extending in the second direction, a buffer layer on the cell pad structure and extending to the boundary region, and a first insulating layer on the buffer layer and extending to the boundary region, wherein a first cross-section of each of the cell pad structures perpendicular to the first