US-12628339-B2 - Resistor between dummy flash structures

Abstract

A resistor between dummy flash structures includes a substrate. The substrate includes a resistor region and a flash region. A first dummy memory gate structure and a second dummy memory gate structure are disposed within the resistor region of the substrate. A polysilicon resistor is disposed between the first dummy memory gate structure and the second dummy memory gate structure. The polysilicon resistor contacts the first dummy memory gate structure and the second dummy memory gate structure.

Inventors

• Weichang Liu
• Wang Xiang
• CHIA CHING HSU
• YUNG-LIN TSENG
• Shen-De Wang

Assignees

• UNITED MICROELECTRONICS CORP.

Dates

Publication Date

20260512

Application Date

20230417

Priority Date

20230317

Claims (20)

1. 1 . A resistor between dummy flash structures, comprising: a substrate comprising a resistor region and a flash region; a first dummy memory gate structure and a second dummy memory gate structure disposed within the resistor region of the substrate; a polysilicon resistor disposed between the first dummy memory gate structure and the second dummy memory gate structure, and the polysilicon resistor contacting the first dummy memory gate structure and the second dummy memory gate structure; and a first dummy select gate structure disposed at one side of the first dummy memory gate structure, and the first dummy select gate structure contacting the first dummy memory gate structure.
2. 2 . The resistor between dummy flash structures of claim 1 , further comprising a silicon oxide layer disposed between the polysilicon resistor and the substrate.
3. 3 . The resistor between dummy flash structures of claim 1 , wherein the first dummy memory gate structure comprises: a first dummy memory gate disposed within the resistor region; a silicon oxide-silicon nitride-silicon oxide stacked layer disposed between the first dummy memory gate and the substrate; and two insulating layers respectively disposed at two sides of the first dummy memory gate and contacting the first dummy memory gate.
4. 4 . The resistor between dummy flash structures of claim 1 , further comprising a split-gate memory, wherein the split-gate memory comprises: a first memory gate structure; and a first select gate structure disposed at a second side of the first memory gate structure.
5. 5 . The resistor between dummy flash structures of claim 4 , wherein the split-gate memory further comprises: a first source/drain doping region disposed within the substrate which is at a first side of the first memory gate structure, wherein the first side is opposed to the second side; and a second source/drain doping region disposed within the substrate which is at a side of the first select gate structure.
6. 6 . The resistor between dummy flash structures of claim 5 , further comprising a second memory gate structure disposed at the first side of the first memory gate structure, wherein a first shortest distance is between the second memory gate structure and the first memory gate structure, a second shortest distance is between the first dummy memory gate structure and the second dummy memory gate structure, and the second shortest distance is smaller than the first shortest distance.
7. 7 . The resistor between dummy flash structures of claim 4 , wherein the first dummy gate structure comprises a first dummy memory gate, the first memory gate structure comprises a first memory gate, and the first dummy memory gate and the first memory gate are made of the same material.
8. 8 . The resistor between dummy flash structures of claim 7 , wherein the first dummy memory gate and the first memory gate are made of polysilicon.
9. 9 . The resistor between dummy flash structures of claim 7 , wherein the first dummy gate structure further comprises a silicon oxide layer disposed between the first dummy memory gate and the substrate, and wherein the silicon oxide layer extends from the first dummy memory gate structure, the silicon oxide layer is positioned beneath the polysilicon resistor, and the polysilicon resistor contacts the silicon oxide layer.
10. 10 . The resistor between dummy flash structures of claim 4 , wherein the first memory gate structure comprises: a first memory gate disposed within the flash region of the substrate; and a silicon oxide-silicon nitride-silicon oxide stacked layer disposed between the first memory gate and the substrate.
11. 11 . A resistor between dummy flash structures, comprising: a substrate comprising a resistor region and a flash region; a first dummy memory gate structure and a second dummy memory gate structure disposed within the resistor region of the substrate; a polysilicon resistor disposed between the first dummy memory gate structure and the second dummy memory gate structure, and the polysilicon resistor contacting the first dummy memory gate structure and the second dummy memory gate structure; and a split-gate memory, wherein the split-gate memory comprises: a first memory gate structure; and a first select gate structure disposed at a second side of the first memory gate structure.
12. 12 . The resistor between dummy flash structures of claim 11 , further comprising a first dummy select gate structure disposed at one side of the first dummy memory gate structure, and the first dummy select gate structure contacting the first dummy memory gate structure.
13. 13 . The resistor between dummy flash structures of claim 11 , further comprising a silicon oxide layer disposed between the polysilicon resistor and the substrate.
14. 14 . The resistor between dummy flash structures of claim 11 , wherein the first dummy memory gate structure comprises: a first dummy memory gate disposed within the resistor region; a silicon oxide-silicon nitride-silicon oxide stacked layer disposed between the first dummy memory gate and the substrate; and two insulating layers respectively disposed at two sides of the first dummy memory gate and contacting the first dummy memory gate.
15. 15 . The resistor between dummy flash structures of claim 11 , wherein the split-gate memory further comprises: a first source/drain doping region disposed within the substrate which is at a first side of the first memory gate structure, wherein the first side is opposed to the second side; and a second source/drain doping region disposed within the substrate which is at a side of the first select gate structure.
16. 16 . The resistor between dummy flash structures of claim 15 , further comprising a second memory gate structure disposed at the first side of the first memory gate structure, wherein a first shortest distance is between the second memory gate structure and the first memory gate structure, a second shortest distance is between the first dummy memory gate structure and the second dummy memory gate structure, and the second shortest distance is smaller than the first shortest distance.
17. 17 . The resistor between dummy flash structures of claim 11 , wherein the first dummy gate structure comprises a first dummy memory gate, the first memory gate structure comprises a first memory gate, and the first dummy memory gate and the first memory gate are made of the same material.
18. 18 . The resistor between dummy flash structures of claim 17 , wherein the first dummy memory gate and the first memory gate are made of polysilicon.
19. 19 . The resistor between dummy flash structures of claim 17 , wherein the first dummy gate structure further comprises a silicon oxide layer disposed between the first dummy memory gate and the substrate, and wherein the silicon oxide layer extends from the first dummy memory gate structure, the silicon oxide layer is positioned beneath the polysilicon resistor, and the polysilicon resistor contacts the silicon oxide layer.
20. 20 . The resistor between dummy flash structures of claim 1 , wherein the first memory gate structure comprises: a first memory gate disposed within the flash region of the substrate; and a silicon oxide-silicon nitride-silicon oxide stacked layer disposed between the first memory gate and the substrate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistor, and more particularly to a resistor disposed between dummy flash structures. 2. Description of the Prior Art A resistor is a passive electronic component which is used to limit current flow passing through a circuit. A resistor works by converting electrical energy into heat to reduce the current flow through the resistor. Resistors are present in almost all electronic circuits and are critical in controlling current and voltage in a circuit. In the modern semiconductor industry, resistors are used in analog circuits such as filters, amplifiers, digital-to-analog converters and analog-to-digital converters. Currently, resistors are formed by implanting or diffusing ions in to substrate regions. However, such resistors occupied a lot of space. In addition, temperature has a strong influence on the resistance value of these resistors. Therefore, there is a need for a resistor which has smaller size, simpler manufacturing process and more stable performance. SUMMARY OF THE INVENTION In view of this, a polysilicon resistor between dummy flash structures is provided. The polysilicon resistor is formed along with the fabricating process of a split-gate memory, and the polysilicon resistor has a smaller size comparing to conventional resistors formed by doping or diffusion. According to a preferred embodiment of the present invention, a resistor between dummy flash structures includes a substrate includes a resistor region and a flash region. A first dummy memory gate structure and a second dummy memory gate structure are disposed within the resistor region of the substrate. A polysilicon resistor is disposed between the first dummy memory gate structure and the second dummy memory gate structure, and the polysilicon resistor contacts the first dummy memory gate structure and the second dummy memory gate structure. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 depicts a resistor between dummy flash structures according to a preferred embodiment of the present invention. FIG. 2 to FIG. 5 depict a fabricating method of a resistor between dummy flash structures according to a preferred embodiment of the present invention, wherein: FIG. 2 depicts a substrate with dummy memory gate structures and memory gate structures thereon; FIG. 3 shows a continuous stage of FIG. 2; FIG. 4 shows a continuous stage of FIG. 3; FIG. 5 shows a continuous stage of FIG. 4; and FIG. 6 shows a continuous stage of FIG. 5. DETAILED DESCRIPTION FIG. 1 depicts a resistor between dummy flash structures according to a preferred embodiment of the present invention. As shown in FIG. 1, a resistor between dummy flash structures includes a substrate 10. The substrate 10 is divided into a resistor region R and a flash region F. Numerous dummy memory gate structures such as a first dummy memory gate structure DM1 and a second dummy memory gate structure DM2 are disposed within the resistor region R of the substrate 10. The first dummy memory gate structure DM1 includes a first dummy memory gate DG1, a silicon oxide-silicon nitride-silicon oxide stacked layer 12a and two insulating layers 14a/14b. The first dummy memory gate DG1 is disposed within the resistor region R of the substrate 10. The silicon oxide-silicon nitride-silicon oxide stacked layer 12a is disposed between the first dummy memory gate DG1 and the substrate 10. Two insulating layers 14a/14b are respectively disposed at two sides of the first dummy memory gate DG1 and contact the first dummy memory gate DG1. The insulating layers 14a/14b can be stacked layers formed by silicon oxide and silicon nitride. The silicon oxide within the aforesaid stacked layers contacts the first dummy memory gate DG1. The second dummy memory gate DM2 includes a second dummy memory gate DG2, a silicon oxide-silicon nitride-silicon oxide stacked layer 12b and two insulating layers 14c/14d. The second dummy memory gate DG2 is disposed within the resistor region R of the substrate 10, and at one side of the first dummy memory gate DG1. The silicon oxide-silicon nitride-silicon oxide stacked layer 12b is disposed between the second dummy memory gate DG2 and the substrate 10. Two insulating layers 14c/14d are respectively disposed at two sides of the second dummy memory gate DG2 and contact the second dummy memory gate DG2. It should be noted that the structure of the first dummy memory gate structure DM1 and the structure of the second dummy memory gate structure DM2 within the resistor region R are not limited to the structures mentioned above. Other types of gate structures of 1.5T embedded split-gate flash can also be applied to the first dummy memory gate structure DM1