US-12628340-B2 - Photolithographic exposure method for memory

US12628340B2US 12628340 B2US12628340 B2US 12628340B2US-12628340-B2

Abstract

A photolithographic exposure method for a memory. In a photolithographic process for making a memory, when exposure is performed by using a mask, regions with different exposure dimension requirements on the memory are divided into different exposure groups. Regions with the same exposure resolution requirement are divided into the same group. Different exposure modes of exposure that are capable of correspondingly satisfying resolution requirements of each group are performed to different groups during exposure. During exposure, different illumination modes are adopted to perform exposure. Firstly, a first exposure mode is adopted to perform exposure to a memory array cell exposure group, then a wafer is kept stationary on a supporting platform, and then a second exposure mode is adopted to perform exposure to the other structure exposure group; after the exposure of all groups is completed, one-step development is performed to complete pattern transfer.

Inventors

Lei Wang

Assignees

Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Dates

Publication Date: 20260512
Application Date: 20220608
Priority Date: 20210609

Claims (10)

1 . A photolithographic exposure method for a memory, wherein in a photolithographic process for making a memory, when exposure is performed by using a mask, regions with different exposure dimension requirements on the memory are divided into different exposure groups; the division of the exposure groups is based on different exposure resolution requirements, regions with the same exposure resolution requirement are divided into the same group, and patterns on the mask are divided into a plurality of exposure groups according to different exposure illumination requirements; and during exposure, different exposure modes of exposure that are capable of correspondingly satisfying resolution requirements of each group are respectively performed to the exposure groups with different exposure resolution requirements.
2 . The photolithographic exposure method for the memory according to claim 1 , wherein the memory comprises memory array cell regions and other structure regions, and the memory array cell regions and other structure parts are divided into different exposure regions to divide the mask into different exposure groups which comprise a memory array cell exposure group of the memory and other structure exposure group formed by patterns of structures except memory array cells on the memory; patterns of the memory array cell exposure group have the highest pattern density, and patterns of the other structure exposure group have a lower pattern density than the memory array cell exposure group.
3 . The photolithographic exposure method for the memory according to claim 2 , wherein the other structure exposure group of the memory comprises a logic device region and an IO region.
4 . The photolithographic exposure method for the memory according to claim 2 , wherein different illumination modes are adopted to perform exposure: firstly, a first exposure mode is adopted to perform exposure to the memory array cell exposure group with the higher pattern density, then a wafer is kept stationary on a supporting platform, and then a second exposure mode is adopted to perform exposure to the other structure exposure group with the lower pattern density; after the different sequential exposure respectively performed to the different exposure groups is fully completed, one-step development is performed to complete transfer of all patterns.
5 . The photolithographic exposure method for the memory according to claim 4 , wherein the first exposure mode is an exposure mode with a higher resolution for dense patterns, and the second exposure mode has a better resolution for relatively sparse pattern regions.
6 . The photolithographic exposure method for the memory according to claim 5 , wherein the first exposure mode comprises polarized illumination and off-axis illumination.
7 . The photolithographic exposure method for the memory according to claim 1 , wherein by performing the different exposure modes of exposure to the different groups, there is no overlapping region between the exposed patterns, and the different exposure operations are independent of each other without needing any additional correction; each exposure using the same mask.
8 . The photolithographic exposure method for the memory according to claim 4 , wherein the illumination modes of two or more times of exposure are different, and a conflict between requirements of the patterns in different exposure regions on the photolithographic process does not need to be considered.
9 . The photolithographic exposure method for the memory according to claim 4 , wherein during exposure, a sequence of different exposure for different exposure groups is capable of being adjusted freely, and the second exposure mode is capable of being adjusted prior to the first exposure mode; the groups are capable of being divided into more exposure groups according to spans of dimension ranges of devices on a chip or different gradients of density, and more exposure modes are selected correspondingly.
10 . The photolithographic exposure method for the memory according to claim 1 , wherein the exposure method is applicable to all chips having regions with different densities and having different exposure resolution requirements.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Chinese patent application No. CN 202110641291.2, filed at CNIPA on Jun. 9, 2021, and entitled “PHOTOLITHOGRAPHIC EXPOSURE METHOD FOR MEMORY”, the disclosure of which is incorporated herein by reference in entirety. TECHNICAL FIELD The present invention relates to the field of processes for manufacturing semiconductor devices, in particular to a photolithographic exposure method for a memory. BACKGROUND In a process for manufacturing a memory, the dimension reduction of memory cells is mainly subject to the limit resolution of a photolithographic process. In order to achieve the limit resolution, a Resolution Enhancement Technique (RET) is usually used. RET is to determine the optimum illumination condition through simulation calculation according to the existing mask design pattern, so as to realize the largest common process window, and this part of the work is usually completed at the early stage of research and development of a new photolithographic process. Common RETs include Off-Axis Illumination (OAI), Optical Proximity Correction (OPC), Phase-Shifting Mask (PSM), Sub-Resolution Assistant Feature (SRAF), and so on. Most RETs involve changing the shape and phase of a mask to some extent, so as to improve the quality of pattern transfer. RETs, such as polarized illumination and OAI, are optimized aiming at dense patterns and have a better resolution, but become poorer for patterns with other dimensions. Curves illustrated in FIG. 1 reflect DOF relationships between traditional illumination, polarized illumination and off-axis illumination, and device dimension. DOF represents depth of focus, or is called depth of field, which refers to a range of a segment of focal plane in which a lithography machine can image clearly after focusing. Since there are not only memory cells in a memory chip, but also many other types of devices, such as digital logic control, IO and decoding circuit, referring to FIG. 2, CD (feature dimension or critical dimension) requirements of different functional units and devices are completely inconsistent with patterns. A memory array in a memory belongs to dense pattern region, while a logic region and an IO region belong to relatively sparse pattern regions. These two regions have different requirements on exposure resolution in the photolithographic process. At present, the existing photolithographic process cannot meet the device requirements of different functional units (or regions with different pattern densities) at the same time. In order to achieve the balance, a sacrifice is needed from respective parts, so the reduction of memory array cells is greatly affected by a peripheral circuit. SUMMARY A technical problem to be solved by the present invention is to provide a photolithographic exposure method for a memory, which can reduce the dimension of memory devices under the situation of limited photolithographic capability. In order to solve the problem, the photolithographic exposure method for the memory provided by the present invention includes the following steps: in a photolithographic process for making a memory, when exposure is performed by using a mask, regions with different exposure dimension requirements on the memory are divided into different exposure groups;the division of the exposure groups is based on different exposure resolution requirements, regions with the same exposure resolution requirement are divided into the same group, and patterns on the mask are divided into a plurality of exposure groups according to different exposure illumination requirements;during exposure, different exposure modes of exposure that are capable of correspondingly satisfying resolution requirements of each group and have the smallest influence on other exposure groups are respectively performed to the exposure groups with different exposure resolution requirements. In an embodiment, the memory includes memory array cell regions and other structure regions, and the memory array cell regions and other structure parts are divided into different exposure regions to divide the mask into different exposure groups which include a memory array cell exposure group of the memory and other structure exposure group formed by patterns of structures except memory array cells on the memory; patterns of the memory array cell exposure group have the highest pattern density, and patterns of the other structure exposure group have a lower pattern density than the memory array cell exposure group. In an embodiment, the other structure exposure group of the memory includes a logic device region and an IO region. In an embodiment, different illumination modes are adopted to perform exposure: firstly, a first exposure mode is adopted to perform exposure to the memory array cell exposure group with the higher pattern density, then the wafer is kept stationary on a stage, and then a second exposure mode is adopted to p