US-12628341-B2 - Semiconductor device including channel layers and method of manufacturing the semiconductor device

Abstract

A semiconductor device including: a stack including first conductive layers and insulating layers that are alternately stacked; second conductive layers disposed on the stack; a separation insulating structure disposed on the stack and configured to insulate the second conductive layers from each other; first channel layers passing through the stack; memory layers enclosing sidewalls of the first channel layers; second channel layers disposed on the stack and passing through the second conductive layers, and each having a width less than a width of the first channel layers; gate insulating layers enclosing sidewalls of the second channel layers; and third channel layers configured to respectively couple the first channel layers with the second channel layers and extending into the second channel layers.

Inventors

• Kang Sik Choi

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260512

Application Date

20210325

Priority Date

20200929

Claims (20)

1. 1 . A semiconductor device comprising: a stack including first conductive layers and insulating layers that are alternately stacked; second conductive layers disposed on the stack; a separation insulating structure disposed on the stack and laterally separating the second conductive layers to insulate the second conductive layers from each other; first channel layers passing through the stack; memory layers extending vertically along the first channel layers; second channel layers disposed on the stack and passing through the second conductive layers, and each having a width less than a width of the first channel layers; gate insulating layers extending vertically along-the second channel layers and extending to sidewalls of the memory layers to be in physical contact with the sidewalls of the memory layers; and third channel layers configured to respectively couple the first channel layers with the second channel layers and extending into the second channel layers, wherein at least a portion of each of the second conductive layers overlaps at least a portion of each of the first channel layers, and wherein at least a portion of an outer side surface of each of the second channel layers is in contact with the corresponding third channel layer.
2. 2 . The semiconductor device according to claim 1 , wherein the memory layers contact with the second conductive layers.
3. 3 . The semiconductor device according to claim 1 , wherein each of the gate insulating layers comprises: a first portion interposed between the second channel layers and the memory layers and being in contact with the sidewalls of the memory layers; and a second portion interposed between the second channel layers and the second conductive layers, wherein the first portion protrudes farther toward one of the memory layers than the second portion.
4. 4 . The semiconductor device according to claim 3 , wherein the first portion has a width greater than a width of the second portion.
5. 5 . The semiconductor device according to claim 1 , wherein each of the third channel layers comprises: a first portion in contact with the corresponding first channel layer; and a second portion in contact with the corresponding second channel layer.
6. 6 . The semiconductor device according to claim 1 , wherein the third channel layers extends between outer surfaces of the second channel layers and inner surfaces of the first channel layers.
7. 7 . The semiconductor device according to claim 5 , wherein the first portion has a width greater than a width of the second portion.
8. 8 . The semiconductor device according to claim 5 , wherein an upper surface of the second portion of each of the third channel layers and an upper surface of the corresponding second channel layer are disposed substantially on a same plane.
9. 9 . The semiconductor device according to claim 1 , wherein each of the second conductive layers comprises: a first portion disposed on the stack; and second portions respectively surrounding the second channel layers and protruding into the stack toward the first channel layers.
10. 10 . The semiconductor device according to claim 9 , wherein the second portions contact with the memory layers.
11. 11 . The semiconductor device according to claim 9 , wherein an outer wall of each of the second portions is aligned with an outer wall of the corresponding memory layer.
12. 12 . The semiconductor device according to claim 1 , wherein at least a portion of at least one of the second channel layers is disposed at the same level as at least one of the first channel layers and at least one of the third channel layers.
13. 13 . The semiconductor device according to claim 12 , wherein the at least one of the second channel layers is in contact with the at least one of the third channel layers, and wherein the at least one of the second channel layers is not in contact with the at least one of the first channel layers.
14. 14 . The semiconductor device according to claim 12 , wherein the at least one of the first channel layers is in contact with the at least one of the third channel layers.
15. 15 . A semiconductor device comprising: a stack including word lines and insulating layers that are alternately stacked; first channel layers passing through the stack; memory layers extending vertically along the first channel layers; second channel layers disposed on the stack; gate insulating layers extending vertically along the second channel layers; third channel layers configured to respectively couple the first channel layers with the second channel layers; select lines each comprising a first portion disposed on the stack, and second portions respectively enclosing the second channel layers and protruding into the stack toward the first channel layers; and a separation insulating structure disposed on the stack and laterally separating the select lines to insulate the select lines from each other, wherein at least a portion of each of the second portions overlaps at least a portion of each of the first channel layers, wherein the gate insulating layers extend to sidewalls of the memory layers to be in physical contact with the sidewalls of the memory layers, wherein at least a portion of an outer side surface of each of the second channel layers is in contact with the corresponding third channel layer, and wherein at least a portion of at least one of the second channel layers is disposed at the same level as at least one of the first channel layers and at least one of the third channel layers.
16. 16 . The semiconductor device according to claim 15 , wherein the second portions of the select lines contact with the memory layers.
17. 17 . The semiconductor device according to claim 15 , wherein an outer wall of each of the second portions is aligned with an outer wall of the corresponding memory layer.
18. 18 . The semiconductor device according to claim 15 , wherein each of the second channel layers has a width less than a width of each of the first channel layers.
19. 19 . The semiconductor device according to claim 15 , wherein each of the gate insulating layers comprises: a first portion interposed between the second channel layers and the memory layers and being in contact with the sidewalls of the memory layers; and a second portion interposed between the second channel layers and the select lines, wherein the first portion protrudes farther toward one of the memory layers than the second portion.
20. 20 . The semiconductor device according to claim 19 , wherein the first portion of each of the gate insulating layers has a width greater than a width of the second portion.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2020-0126714, filed on Sep. 29, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. BACKGROUND 1. Technical Field Various embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor device. 2. Related Art Recently, as the improvement of integration of a two-dimensional memory element including memory cells formed in a single layer on a substrate is limited, a three-dimensional (3D) memory element including memory cells stacked in a vertical direction on a substrate has been proposed. To improve the operational reliability of such a memory element having a three-dimensional structure, various structures and manufacturing methods have been developed. SUMMARY An embodiment of the present disclosure may provide for a semiconductor device may include: a stack including first conductive layers and insulating layers that are alternately stacked; second conductive layers disposed on the stack; a separation insulating structure disposed on the stack and configured to insulate the second conductive layers from each other; first channel layers passing through the stack; memory layers enclosing sidewalls of the first channel layers; second channel layers disposed on the stack and passing through the second conductive layers, and each having a width less than a width of the first channel layers; gate insulating layers enclosing sidewalls of the second channel layers; and third channel layers configured to respectively couple the first channel layers with the second channel layers and extending into the second channel layers. An embodiment of the present disclosure may provide for a semiconductor device may include: a stack including word lines and insulating layers that are alternately stacked; first channel layers passing through the stack; memory layers enclosing sidewalls of the first channel layers; second channel layers disposed on the stack; gate insulating layers enclosing sidewalls of the second channel layers; third channel layers configured to respectively couple the first channel layers with the second channel layers; select lines each comprising a first portion disposed on the stack, and second portions respectively enclosing the second channel layers and protruding into the stack toward the first channel layers; and a separation insulating structure disposed on the stack and configured to insulate the select lines from each other. An embodiment of the present disclosure may provide for a method of manufacturing a semiconductor device, may include: forming a stack including first material layers and second material layers that are alternately stacked; forming a sacrificial layer on the stack; forming a separation insulating structure passing through the sacrificial layer and disposed over the first material layers; forming a first opening passing through the sacrificial layer, the separation insulating structure, and the stack; forming a first channel layer in the first opening; forming a sacrificial spacer coupled with the sacrificial layer in the first opening; forming in the sacrificial spacer a second channel layer having a width less than a width of the first channel layer; and forming in the first opening a third channel layer configured to couple the first channel layer with the second channel layer and extend into the second channel layer. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating the structure of a semiconductor device in accordance with an embodiment of the present disclosure. FIGS. 2A, 2B, and 2C are diagrams illustrating the structure of a semiconductor device in accordance with an embodiment of the present disclosure. FIGS. 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, and 15B are diagrams for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present disclosure. FIGS. 16A, 16B, 16C, 16D, 16E, 16F, 16G, 16H, and 16I are views illustrating a method of manufacturing the semiconductor device according to an embodiment of the present disclosure. FIG. 17 is a diagram illustrating a memory system in accordance with an embodiment of the present disclosure. FIG. 18 is a diagram illustrating a memory system in accordance with an embodiment of the present disclosure. FIG. 19 is a diagram illustrating a memory system in accordance with an embodiment of the present disclosure. FIG. 20 is a diagram illustrating a memory system in accordance with an embodiment of the present disclosure. FIG. 21 is a diagram illustrating a memory system in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION Specific structural or functional desc