US-12628342-B2 - Methods used in forming a memory array comprising strings of memory cells including selective depositing of silicon

US12628342B2US 12628342 B2US12628342 B2US 12628342B2US-12628342-B2

Abstract

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A vertical stack comprising alternating first tiers and second tiers is formed above the conductor tier. Channel-material strings extend through the alternating tiers. Conducting material is formed in a lower of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The forming of the conducting material comprises forming conductive material in the lower first tier against the channel material of the individual channel-material strings. The conductive material comprises an upper portion and a lower portion having a void-space vertically there-between. The void-space comprises an exposed silicon-containing surface. Silicon is selectively deposited into the void-space onto and from the exposed silicon-containing surface. Other embodiments, including structure independent of method, are disclosed.

Inventors

John D. Hopkins
Nancy M. Lomeli
Jordan D. Greenlee

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260512
Application Date: 20220601

Claims (19)

1 . A method used in forming a memory array comprising strings of memory cells, comprising: forming a conductor tier comprising conductor material on a substrate; forming laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier, channel-material strings extending through the first tiers and the second tiers; and forming conducting material in a lower of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier, the forming of the conducting material comprising: forming conductive material in the lower first tier in the laterally-spaced-memory-block regions against the channel material of the individual channel-material strings, the conductive material comprising an upper portion and a lower portion in the laterally-spaced-memory-block regions and having a void-space in the laterally-spaced-memory-block regions vertically between the upper and lower portions, the void-space comprising an exposed elemental-silicon-containing surface in the laterally-spaced-memory-block regions; and selectively depositing silicon into the void-space in the laterally-spaced-memory-block regions onto and from the exposed elemental-silicon-containing surface and not onto exposed non-elemental-silicon-containing surfaces, the selectively-deposited silicon completely filling the void-space in the laterally-spaced-memory-block regions.
2 . The method of claim 1 wherein the upper portion, the lower portion, and the exposed silicon-containing surface comprise conductively-doped polysilicon.
3 . The method of claim 1 wherein the silicon-containing surface on and from which the silicon is selectively deposited comprises a floor of the void-space.
4 . The method of claim 1 wherein the silicon-containing surface on and from which the silicon is selectively deposited comprises a ceiling of the void-space.
5 . The method of claim 1 wherein the silicon-containing surface on and from which the silicon is selectively deposited comprises a lateral sidewall of the void-space.
6 . The method of claim 1 wherein the silicon-containing surface on and from which the silicon is selectively deposited comprises a floor of the void-space, a ceiling of the void-space, and a lateral sidewall of the void-space.
7 . The method of claim 1 wherein the first tiers are conductive tiers in a finished circuitry construction and the second tiers are insulative tiers in the finished circuitry construction, the void-space being in a lowest of the conductive tiers.
8 . The method of claim 1 wherein the selectively depositing is of epitaxial silicon.
9 . The method of claim 1 wherein the selectively depositing is of polysilicon.
10 . The method of claim 1 wherein the selectively depositing is of amorphous silicon and further comprising annealing the amorphous silicon to form polysilicon therefrom.
11 . The method of claim 1 wherein, the conductive material is crystalline in a finished circuitry construction; and the selectively-deposited silicon in the finished circuitry construction is crystalline and has an average maximum-straight-line distance across individual of its crystal grains that is at least 20% greater than an average maximum-straight-line distance across individual crystal grains of the crystalline conductive material.
12 . The method of claim 11 wherein the average maximum-straight-line distance across the individual crystal grains of the selectively-deposited silicon in the finished circuitry construction is no more than 10,000% greater than the average maximum-straight-line distance across the individual crystal grains of the crystalline conductive material.
13 . The method of claim 1 wherein the selectively-deposited silicon is conductive at least in a finished circuitry construction.
14 . A method used in forming a memory array comprising strings of memory cells, comprising: forming a conductor tier comprising conductor material on a substrate; forming laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier, channel-material strings extending through the first tiers and the second tiers; and forming conducting material in a lower of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier, the forming of the conducting material comprising: forming undoped semiconductive material in the lower first tier directly against the channel material of the individual channel-material strings, the undoped semiconductive material having more than 0 atomic dopant concentration and less than 0.01 atomic percent dopant therein; forming conductive material in the lower first tier directly against the undoped semiconductive material, the conductive material comprising an upper portion and a lower portion having a void-space vertically there-between, the void-space comprising an exposed elemental-silicon-containing surface; and selectively depositing silicon into the void-space onto and from the exposed elemental-silicon-containing surface.
15 . The method of claim 14 wherein the undoped semiconductive material comprises polysilicon.
16 . The method of claim 14 wherein the undoped semiconductive material has 1×10 7 atoms/cm 3 of dopant therein.
17 . The method of claim 14 wherein the undoped semiconductive material is not intrinsically conductive in a finished construction of the memory array, yet is sufficiently thin such that electrical conduction occurs there-through as a result of such thinness.
18 . The method of claim 17 wherein the undoped semiconductive material forms ohmic contact with the conductive material and with the channel material.
19 . The method of claim 14 wherein the initially-formed undoped semiconductive material becomes and is intrinsically conductive in a finished construction of the memory array.

Description

TECHNICAL FIELD Embodiments disclosed herein pertain to memory arrays comprising strings of memory cells and to methods used in forming a memory array comprising strings of memory cells. BACKGROUND Memory is one type of integrated circuitry and is used in computer systems for storing data. Memory may be fabricated in one or more arrays of individual memory cells. Memory cells may be written to, or read from, using digitlines (which may also be referred to as bitlines, data lines, or sense lines) and access lines (which may also be referred to as wordlines). The sense lines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell may be uniquely addressed through the combination of a sense line and an access line. Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information. A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region therebetween. A conductive gate is adjacent the channel region and separated there-from by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structure, for example a reversibly programmable charge-storage region as part of the gate construction between the gate insulator and the conductive gate. Flash memory is one type of memory and has numerous uses in modern computers and devices. For instance, modern personal computers may have BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid state drives to replace conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the devices for enhanced features. Memory arrays may be arranged in memory pages, memory blocks and partial blocks (e.g., sub-blocks), and memory planes, for example as shown and described in any of U.S. Patent Application Publication Nos. 2015/0228651, 2016/0267984, and 2017/0140833. The memory blocks may at least in part define longitudinal outlines of individual wordlines in individual wordline tiers of vertically-stacked memory cells. Connections to these wordlines may occur in a so-called “stair-step structure” at an end or edge of an array of the vertically-stacked memory cells. The stair-step structure includes individual “stairs” (alternately termed “steps” or “stair-steps”) that define contact regions of the individual wordlines upon which elevationally-extending conductive vias contact to provide electrical access to the wordlines. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1-4 are diagrammatic cross-sectional views of portions of a construction that will comprise an array of elevationally-extending strings of memory cells in accordance with an embodiment of the invention. FIGS. 5-22 are diagrammatic sequential sectional and/or enlarged views of the construction of FIGS. 1-4, or portions thereof or alternate and/or additional embodiments, in process in accordance with some embodiments of the invention. DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS Embodiments of the invention encompass methods used in forming a memory array, for example an array of NAND or other memory cells that may have at least some peripheral control circuitry under the array (e.g., CMOS-under-array). Embodiments of the invention encompass so-called “gate-last” or “replacement-gate” processing, so-called “gate-first” processing, and other processing whether existing or future-developed independent of when transistor gates are formed. Embodiments of the invention also encompass integrated circuitry comprising a memory array comprising strings of memory cells (e.g., NAND architecture) independent of method of manufacture. First example method embod