US-12628343-B2 - Semiconductor devices and data storage systems including the same

US12628343B2US 12628343 B2US12628343 B2US 12628343B2US-12628343-B2

Abstract

A semiconductor memory device includes: a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure may include: a second substrate having a first region and a second region; a substrate insulating layer extending through the second substrate; a landing pad extending through the substrate insulating layer; gate electrodes, each having a gate pad region on the second region having an exposed upper surface; and a gate contact plug extending through the gate pad region of at least one of the gate electrodes and into the landing pad. The landing pad may include a pad portion that is surrounded by an internal side surface of the substrate insulating layer, and a via portion extending from the pad portion to the lower interconnection structure.

Inventors

Kyeonghoon Park
Inhwan Baek
Jaebok BAEK
Jeehoon HAN
Seungyoon Kim
Heesuk KIM
Byoungjae Park
JONGSEON AHN
Jumi Yun

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20230302
Priority Date: 20220523

Claims (20)

1 . A semiconductor device comprising: a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and a second semiconductor structure on the first semiconductor structure, the second semiconductor structure comprising: a second substrate having a first region and a second region; a substrate insulating layer that extends through the second substrate; a landing pad that extends through the substrate insulating layer; gate electrodes spaced apart from each other and stacked on the first region in a first direction and extending with different lengths in a second direction on the second region, each of the gate electrodes including a gate pad region on the second region and having an exposed upper surface; and a gate contact plug that extends through the gate pad region of at least one of the gate electrodes and extends into the landing pad in the first direction, wherein the landing pad includes a pad portion that is surrounded by an internal side surface of the substrate insulating layer, and wherein the landing pad includes a via portion that extends from the pad portion to the lower interconnection structure of the first semiconductor structure.
2 . The semiconductor device of claim 1 , wherein the pad portion is disposed on a level the same as or higher than a level of a lower surface of the second substrate, and wherein the internal side surface of the substrate insulating layer is in contact with the pad portion of the landing pad and an external side surface of the substrate insulating layer is in contact with the second substrate in the second region.
3 . The semiconductor device of claim 1 , wherein the substrate insulating layer has an annular shape in the second region.
4 . The semiconductor device of claim 1 , wherein the substrate insulating layer separates the landing pad and the second substrate from each other.
5 . The semiconductor device of claim 1 , wherein a lower surface of the substrate insulating layer is at a level that is lower than a level of a lower surface of the second substrate.
6 . The semiconductor device of claim 1 , wherein the pad portion of the landing pad is coplanar with the second substrate in the first direction, and wherein the via portion of the landing pad is at a level that is lower than a lower surface of the second substrate.
7 . The semiconductor device of claim 1 , wherein the landing pad includes tungsten (W), copper (Cu), aluminum (Al), molybdenum (Mo), or alloys thereof.
8 . The semiconductor device of claim 1 , further comprising: a channel structure on the first region and extending in the first direction through the gate electrodes, the channel structure including a channel layer, wherein an upper surface of the channel structure is at substantially the same level as an upper surface of the gate contact plug.
9 . The semiconductor device of claim 8 , wherein a lower surface of the channel structure is at substantially the same level as a lower surface of the gate contact plug.
10 . The semiconductor device of claim 1 , wherein the second semiconductor structure comprises: a horizontal insulating layer that is parallel to lower portions of the gate electrodes on a portion of the second substrate; and a horizontal conductive layer on the horizontal insulating layer, wherein the pad portion of the landing pad includes a first pad portion coplanar in the first direction with the second substrate, a second pad portion coplanar in the first direction with the horizontal insulating layer, and a third pad portion coplanar in the first direction with the horizontal conductive layer, and wherein the second and third pad portions are a dummy pad region.
11 . The semiconductor device of claim 10 , wherein: the second pad portion includes the same material as the horizontal insulating layer, and the second pad portion surrounds the gate contact plug and is spaced apart from the horizontal insulating layer.
12 . The semiconductor device of claim 1 , wherein: the substrate insulating layer includes an inner substrate insulating layer that extends into the second substrate in the second region, and an outer substrate insulating layer, outside the second substrate in the second region, and the semiconductor device further comprises: an outer landing pad that extends through the outer substrate insulating layer; and a through-contact plug that is spaced apart from the gate electrodes and that extends into the outer landing pad in the first direction.
13 . The semiconductor device of claim 12 , wherein the outer landing pad includes a pad portion that is surrounded by the outer substrate insulating layer, and a via portion that extends from the pad portion to the lower interconnection structure, and a lower end of the through-contact plug is in contact with the pad portion and is at a level that is higher than a level of the via portion.
14 . A semiconductor device comprising: a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and a second semiconductor structure on the first semiconductor structure, the second semiconductor structure comprising: a second substrate having a first region and a second region; an inner substrate insulating layer having a ring shape and extending through the second substrate; gate electrodes spaced apart from each other and stacked on the first region in a first direction and extending with different lengths in a second direction, each of the gate electrodes including a gate pad region having an exposed upper surface on the second region; and a gate contact plug extending in the first direction through the gate pad region of each of the gate electrodes through a space within the ring shape of the inner substrate insulating layer.
15 . The semiconductor device of claim 14 , wherein a width of the inner substrate insulating layer is substantially uniform along a perimeter of the ring shape.
16 . The semiconductor device of claim 14 , wherein the ring shape of the inner substrate insulating layer is a circular ring shape, a polygonal ring shape, or a corner-rounded polygonal ring shape.
17 . The semiconductor device of claim 14 , wherein an external side surface of the inner substrate insulating layer is in contact with the second substrate, an internal side surface of the inner substrate insulating layer is in contact with a landing pad coplanar with the second substrate in the first direction, the gate contact plug is in contact with the landing pad, and the inner substrate insulating layer separates the second substrate and the landing pad from each other.
18 . The semiconductor device of claim 14 , further comprising: a plurality of support structures extending in the first direction through the gate electrodes, and adjacent to the gate contact plug, wherein in a plan view, the inner substrate insulating layer surrounds the gate contact plug and is between the plurality of support structures and the gate contact plug.
19 . A data storage system comprising: a semiconductor storage device including a first semiconductor structure, a second semiconductor structure, an input/output pad, the first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices, the second semiconductor structure on the first semiconductor structure, the input/output pad electrically connected to the circuit devices; and a controller electrically connected to the semiconductor storage device through the input/output pad and configured to control the semiconductor storage device, wherein the second semiconductor structure comprises: a second substrate having a first region and a second region; an inner substrate insulating layer having a ring shape and extending through the second substrate; gate electrodes spaced apart from each other and stacked on the first region in a first direction and having different lengths in a second direction, each of the gate electrodes including a gate pad region on the second region having an exposed upper surface; and a gate contact plug extending in the first direction through the gate pad region of at least one of the gate electrodes through a space within the ring shape of the inner substrate insulating layer.
20 . The data storage system of claim 19 , further comprising: a landing pad including a pad portion, surrounded by an internal side surface of the inner substrate insulating layer, and a via portion extending from the pad portion to the lower interconnection structure, wherein the gate contact plug is in contact with the pad portion, and wherein a lower end of the gate contact plug is at a level that is higher than a level of the via portion.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application claims benefit of priority to Korean Patent Application No. 10-2022-0062681 filed on May 23, 2022, in the Korean Intellectual Property Office, and the entire contents of the above-identified application are incorporated by reference herein. BACKGROUND The present disclosure relates to semiconductor devices and data storage systems including the same. In data storage systems that use or require data storage, there is increasing demand for semiconductor devices which may store high-capacity data. Accordingly, research into methods of increasing data storage capacity of a semiconductor device has been conducted. For example, a semiconductor device including three-dimensionally arranged memory cells, rather than two-dimensionally arranged memory cells, has been proposed as a method of increasing data storage capacity of a semiconductor device. SUMMARY Aspects of the present disclosure provide semiconductors device having improved productivity and electrical characteristics and data storage systems including the same. According to some example embodiments, a semiconductor device includes: a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure may include: a second substrate having a first region and a second region; a substrate insulating layer that extends through the second substrate; a landing pad that extends through the substrate insulating layer; gate electrodes spaced apart from each other and stacked on the first region in a first direction and extending by different lengths in a second direction on the second region, each of the gate electrodes including a gate pad region on the second region and having an exposed upper surface; and a gate contact plug that extends through the gate pad region of at least one of the gate electrodes and into the landing pad in the first direction. The landing pad may include a pad portion that is surrounded by an internal side surface of the substrate insulating layer, and a via portion that extends from the pad portion to the lower interconnection structure of the first semiconductor structure. According to some example embodiments, a semiconductor device includes: a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure may include: a second substrate having a first region and a second region; an inner substrate insulating layer having a ring shape and extending through the second substrate; gate electrodes spaced apart from each other and stacked on the first region in a first direction and extending with different lengths in a second direction, each of the gate electrodes including a gate pad region having an exposed upper surface on the second region; and a gate contact plug extending in the first direction through the gate pad region of each of the gate electrodes through a space within the ring shape of the inner substrate insulating layer. According to some example embodiments, a semiconductor device includes: a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure may include: a second substrate having a first region and a second region; gate electrodes spaced apart from each other and stacked on the first region and extending on the second region in a section direction by different lengths, each of the gate electrodes including a gate pad region on the second region having an exposed upper surface; a channel structure extending through the gate electrodes, extending in the first direction, and including a channel layer, on the first region; a gate contact plug extending in the first direction through the gate pad regions of each of the gate electrodes; and a plurality of support structures on the second region, the plurality of support structures extending through the gate electrodes, extending in the first direction, and adjacent to the gate contract plug, on the second region. Upper surfaces of the channel structure, the gate contact plug, and each of the plurality of support structures may be at substantially the same level. According to an example embodiment, a data storage system includes: a semiconductor storage device including a first semiconductor structure and a second semiconductor structure, the first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection stru