US-12628344-B2 - Memory device and method of manufacturing memory device

Abstract

There is provided a memory device and a method of manufacturing the memory device. The memory device includes: a wafer including a chip region and an edge region surrounding the chip region; a stack structure including a plurality of insulating layers and a plurality of conductive layers, which are alternately stacked over the chip region; a plurality of channel structures disposed in the stack structure; a first slit penetrating the plurality of insulating layers and the plurality of conductive layers; an upper insulating layer disposed over the edge region; and a plurality of second slits formed in a portion of the upper insulating layer.

Inventors

• Hyun Mi HWANG

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260512

Application Date

20230728

Priority Date

20230130

Claims (8)

1. 1 . A memory device comprising: a wafer including a chip region and an edge region surrounding the chip region; a stack structure including a plurality of insulating layers and a plurality of conductive layers, which are alternately stacked over the chip region; a plurality of channel structures disposed in the stack structure; a first slit penetrating the plurality of insulating layers and the plurality of conductive layers; an upper insulating layer disposed over the edge region; a plurality of second slits formed in a portion of the upper insulating layer, and a plurality of third slits formed in a portion of the upper insulating layer, wherein the plurality of second slits are located between the plurality of third slits and the first slit.
2. 2 . The memory device of claim 1 , wherein the plurality of second slits surround the chip region, and wherein the plurality of second slits are spaced apart from each other.
3. 3 . The memory device of claim 1 , wherein the plurality of second slits and the plurality of third slits are formed in substantially a line shape extending in a first direction, wherein the plurality of second slits are arranged in a second direction intersecting the first direction, and wherein the plurality of third slits are arranged in the second direction.
4. 4 . The memory device of claim 3 , wherein the plurality of third slits are spaced apart from the plurality of second slits in the first direction.
5. 5 . The memory device of claim 3 , wherein the plurality of third slits are spaced apart from the plurality of second slits in a diagonal direction between the first direction and the second direction.
6. 6 . The memory device of claim 1 , further comprising a gap fill layer disposed in the plurality of second slits, wherein the gap fill layer includes at least one of a conductive material and an insulating material.
7. 7 . A memory device comprising: a wafer including a chip region and an edge region surrounding the chip region; a stack structure including a plurality of conductive layers and a plurality of insulating layers, which are alternately stacked over the chip region of the wafer, wherein the stack structure includes a stepped structure comprising end portions of the conductive layers and insulating layers, and wherein each step of the stepped structure includes a pad part including a conductive layer from the plurality of conductive layers and an insulating layer from the plurality insulating layers; a plurality of channel structures disposed in the stack structure; an upper insulating layer formed over the stack structure to cover the stepped structure, the upper insulating layer extending onto the edge region of the wafer; a plurality of contact structures in contact with the plurality of pad parts while being formed in a portion of the upper insulating layer overlapping with the plurality of pad parts; and a slit formed in a portion of the upper insulating layer, the slit overlapping with the edge region of the wafer.
8. 8 . The memory device of claim 7 , further comprising a gap fill layer inside the slit, wherein the gap fill layer includes at least one of a conductive material and an insulating material.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2023-0012065 filed on Jan. 30, 2023, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein. BACKGROUND 1. Technical Field The present disclosure generally relates to a memory device and a method of manufacturing a memory device, and more particularly, to a three-dimensional memory device and a method of manufacturing a three-dimensional memory device. 2. Related Art A memory device may be classified into a volatile memory device in which stored data disappears when the supply of power is interrupted and a nonvolatile memory device in which stored data is retained even when the supply of power is interrupted. The nonvolatile memory device may include a NAND flash memory, a NOR flash memory, a resistive random access memory (ReRAM), a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), and the like. A NAND flash memory system may include a memory device configured to store data and a controller configured to control the memory device. The memory device may include a memory cell array in which data is stored and peripheral circuits configured to perform a program, read or erase operation in response to a command transmitted from the controller. Material layers used in a semiconductor manufacturing process have intrinsic stress, and warpage may occur in a wafer due to stress induced by a material layer deposition process and an annealing process. When warpage occurs in a wafer, separation or cracks between material layers deposited on the wafer may occur. Therefore, the wafer may structurally become unstable, and the operational characteristic or reliability of a semiconductor device may deteriorate. SUMMARY In accordance with an embodiment of the present disclosure, there may be provided a memory device including: a wafer including a chip region and an edge region surrounding the chip region; a stack structure including a plurality of insulating layers and a plurality of conductive layers, which are alternately stacked over the chip region; a plurality of channel structures disposed in the stack structure; a first slit penetrating the plurality of insulating layers and the plurality of conductive layers; an upper insulating layer disposed over the edge region; and a plurality of second slits formed in a portion of the upper insulating layer. In accordance with an embodiment of the present disclosure, there may be provided a memory device including: a wafer including a chip region and an edge region surrounding the chip region; a stack structure including a plurality of conductive layers and a plurality of insulating layers, which are alternately stacked over the chip region of the wafer, wherein the stack structure includes a stepped structure comprising end portions of the conductive layers and insulating layers, and wherein each step of the stepped structure includes a pad part including a conductive layer from the plurality of conductive layers and an insulating layer from the plurality insulating layers; a plurality of channel structures disposed in the stack structure; an upper insulating layer formed over the stack structure to cover the stepped structure, the upper insulating layer extending onto the edge region of the wafer; a plurality of contact structures in contact with the plurality of pad parts while being formed in a portion of the upper insulating layer overlapping with the plurality of pad parts; and a slit formed in a portion of the upper insulating layer, the slit overlapping with the edge region of the wafer. In accordance with an embodiment of the present disclosure, there may be provided a method of manufacturing a memory device, the method including: providing a wafer including a chip region and an edge region surrounding the chip region; forming a stack structure in which a plurality of first material layers and a plurality of second material layers are alternately stacked over the chip region of the wafer; forming a stepped structure by forming a plurality of pad parts by etching portions of the plurality of first material layers and the plurality of second material layers; forming an insulating layer covering the plurality of pad parts, the insulating layer covering at least a portion of the edge region; forming a first slit extending in a vertical direction in the stack structure; and forming a plurality of second slits in the insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS In the drawing figures, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or one or more intervening elements may also be pres