US-12628345-B2 - Method for fabricating the semiconductor memory device

Abstract

A method for fabricating a semiconductor memory device may include the steps of: forming a stacked body on a source layer by alternately stacking a plurality of interlayer dielectric layers and a plurality of gate sacrificial layers; forming a plurality of channel holes through the stacked body, the channel holes each having a lower end extended into the source layer; forming a channel layer along the surfaces of the channel holes, the channel layer including a first region formed in the stacked body and a second region formed in the source layer; and forming a channel passivation layer in the first region to scale down the thickness of the channel layer of the first region.

Inventors

• Yu Jeong Lee
• Dae Hwan YUN
• Gil Bok CHOI

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260512

Application Date

20240212

Priority Date

20210209

Claims (19)

1. 1 . A method for fabricating a semiconductor memory device, the method comprising the steps of: forming a stacked body on a source layer by alternately stacking a plurality of interlayer dielectric layers and a plurality of gate sacrificial layers; forming a plurality of channel holes through the stacked body, the channel holes each having a lower end extended into the source layer; forming a channel layer along the surfaces of the channel holes, the channel layer including a first region formed in the stacked body and a second region formed in the source layer; forming a sacrificial layer on the channel layer of the second region; forming a channel passivation layer in the first region to scale down the thickness of the channel layer of the first region; and removing the sacrificial layer after the channel passivation layer is formed.
2. 2 . The method according to claim 1 , further comprising the step of forming a memory layer on side and bottom surfaces of the channel holes before forming the semiconductor layer, wherein the memory layer is formed as a stacked layer in which a blocking layer, a charge trap layer and a tunnel dielectric layer are stacked.
3. 3 . The method according to claim 1 , further comprising the steps of: forming a core pillar on the channel passivation layer and the channel layer after forming the channel passivation layer, such that the core pillar gap-fills the channel hole; forming a recess by etching the top of the core pillar; expanding the recess by etching the channel passivation layer exposed to a side surface of the recess; and forming a capping layer which gap-fills the expanded recess and is electrically coupled to the channel layer.
4. 4 . The method according to claim 1 , wherein forming the channel layer comprises: forming a semiconductor layer along the surfaces of the channel holes, the semiconductor layer having a first thickness; forming a crystallized semiconductor layer by performing a crystallization anneal process; and etching the crystallized semiconductor layer to have a second thickness smaller than the first thickness, wherein the forming of the semiconductor layer, the crystallization anneal process and the etching are repeatedly performed one or more times.
5. 5 . The method according to claim 4 , further comprising forming a crystallization support layer on the semiconductor layer before performing the crystallization anneal process, wherein the crystallization support layer is removed in the step of etching the crystallized semiconductor layer to have the second thickness.
6. 6 . The method according to claim 5 , wherein the semiconductor layer comprises an amorphous silicon layer or a polycrystalline silicon layer, and the crystallization support layer comprises a silicon-containing dielectric layer.
7. 7 . The method according to claim 1 , wherein the channel passivation layer is formed by selectively oxidizing the surface of the channel layer of the first region through radical oxidation in the first region.
8. 8 . The method according to claim 7 , wherein the channel layer includes a polycrystalline silicon layer, and the channel passivation layer includes a silicon oxide layer.
9. 9 . The method according to claim 1 , wherein the channel passivation layer is formed through radical oxidation using oxygen radicals generated from a process gas in which a hydrogen gas and an oxygen gas are mixed, and formed at a temperature of 600° C. to 800° C. and a pressure of 0.1 torr to 1 torr.
10. 10 . The method according to claim 1 , wherein the channel layer of the first region has a smaller thickness than the channel layer of the second region, after the channel passivation layer is formed.
11. 11 . The method according to claim 1 , wherein the channel layer has a cylinder shape, the channel layer of the first region has a pipe shape, the channel layer of the second region has a cylinder shape, and the channel passivation layer has a pipe shape.
12. 12 . The method according to claim 1 , wherein each of the channel holes has an inclined sidewall, and has a trapezoid-type cross-sectional shape whose top entrance has a larger line width than a bottom surface of the trapezoid-type cross-sectional shape.
13. 13 . The method of claim 1 , further comprising, before forming the passivation layer, forming a sacrificial layer to gap-fill the bottom of the channel hole, forming the passivation layer, and then removing the sacrificial layer.
14. 14 . A method for fabricating a semiconductor memory device, the method comprising the steps of: forming a stacked body including a first region and a second region formed under the first region; forming at least one channel hole in the stacked body; forming a channel layer along inner surfaces of the channel hole to have a first set thickness; and selectively shrinking the channel layer of the first region to have a second set thickness thinner than the first set thickness, wherein the second region includes at least one source layer contacted to the channel layer having the first set thickness.
15. 15 . The method according to claim 14 , wherein the step of the shrinking the channel layer of the first region comprises forming a channel passivation layer on the channel layer of the first region.
16. 16 . The method according to claim 15 , wherein the channel passivation layer is formed by selectively oxidizing a set thickness of the channel layer of the first region.
17. 17 . The method according to claim 16 , wherein the channel passivation layer is formed through a radical oxidation using oxygen radicals generated from a process gas in which a hydrogen gas and an oxygen gas are mixed, and formed at a temperature of 600° C. to 800° C. and a pressure of 0.1 torr to 1 torr.
18. 18 . The method according to claim 14 , further comprising: forming a memory layer along the inner surface of the channel hole before forming the channel layer.
19. 19 . The method according to claim 14 , wherein the first region is formed by alternately stacking a plurality of interlayer dielectric layers and a plurality of gate sacrificial layers.

Description

CROSS-REFERENCES TO RELATED APPLICATION The present application is a continuation of U.S. patent application Ser. No. 17/362,624, filed on Jun. 29, 2021, titled “Semiconductor memory device and method for fabricating the semiconductor memory device” and claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2021-0018105, filed on Feb. 9, 2021, in the Korean Intellectual Property Office, which is incorporated herein by reference in their entirety. BACKGROUND 1. Technical Field Various embodiments generally relate to an electronic device, and more particularly, to a semiconductor memory device and a method for fabricating the semiconductor memory device. 2. Related Art In order to satisfy excellent performance and a low price, which are demanded by consumers, the degree of integration of a semiconductor device needs to be improved. In particular, since the degree of integration of the semiconductor memory device is an important factor to decide the performance and price of a product, various attempts are being made to improve the degree of integration. For example, research is being actively conducted on a 3D semiconductor memory device which includes a plurality of memory cells arranged in a 3D manner, and thus may reduce an area occupied by memory cells per unit area of a substrate. SUMMARY In an embodiment, a method for fabricating a semiconductor memory device may include the steps of: forming a stacked body on a source layer by alternately stacking a plurality of interlayer dielectric layers and a plurality of gate sacrificial layers; forming a plurality of channel holes through the stacked body, the channel holes each having a lower end extended into the source layer; forming a channel layer along the surfaces of the channel holes, the channel layer including a first region formed in the stacked body and a second region formed in the source layer; and forming a channel passivation layer in the first region to scale down the thickness of the channel layer of the first region. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram schematically illustrating a configuration of a semiconductor memory device in accordance with an embodiment. FIG. 2 is a circuit diagram illustrating a part of a memory block of the semiconductor memory device in accordance with an embodiment. FIG. 3 is a perspective view schematically illustrating the semiconductor memory device in accordance with an embodiment. FIG. 4 is a perspective view illustrating the semiconductor memory device in accordance with an embodiment. FIG. 5 is an expanded cross-sectional view of a region ‘A’ illustrated in FIG. 4. FIGS. 6A, 6B, and 6C are plan views of a channel structure, taken along lines I-I′, II-II′ and III-III′ of FIG. 4, respectively. FIG. 7 is a flowchart schematically illustrating a method for fabricating a semiconductor memory device in accordance with an embodiment. FIG. 8 is a flowchart schematically illustrating a method for fabricating a semiconductor memory device in accordance with an embodiment. FIGS. 9A, 9B, 9C, 9D, 9E, 9F, 9G and 9H are cross-sectional views illustrating a method for fabricating a semiconductor memory device in accordance with an embodiment. FIGS. 10A, 10B, 10C and 10D are cross-sectional views illustrating a method for fabricating a semiconductor memory device in accordance with an embodiment. FIGS. 11A, 11B, 11C, 11D, 11E, 11F and 11G are cross-sectional views illustrating a method for fabricating a semiconductor memory device in accordance with an embodiment. FIG. 12 is a block diagram illustrating a configuration of a memory system in accordance with an embodiment. FIG. 13 is a block diagram illustrating a configuration of a computing system in accordance with an embodiment. DETAILED DESCRIPTION Various embodiments are directed to a semiconductor memory device capable of improving operation reliability, and a method for fabricating the semiconductor memory device. The advantages and characteristics of the disclosure and a method for achieving the advantages and characteristics will become clear through the embodiments described in detail with reference to the accompanying drawings. However, the disclosure is not limited to the embodiments disclosed below and may be embodied in different forms. These embodiments are provided so that this disclosure will be thorough and complete, and the scope of the disclosure will be fully conveyed to those skilled in the art. The disclosure is only defined by the scope of claims. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated in order to clarify the description. Through the specification, like reference numerals represent the same components. The embodiments which will be described below provide a semiconductor memory device capable of improving operation reliability, and a method for fabricating the same. The semiconductor memory device may include a nonvolatile semiconductor memory device having a 3D struc