US-12628346-B2 - Semiconductor memory device including a plurality of memory blocks and method of manufacturing the same

US12628346B2US 12628346 B2US12628346 B2US 12628346B2US-12628346-B2

Abstract

A semiconductor memory device may include a plurality of memory blocks and at least one insulation bridge. The plurality of the memory blocks may be defined by a plurality of slits parallel to each other. The at least one insulation bridge may be formed in at least one slit located on at least one side of a memory block of the plurality of memory blocks to support the adjacent memory blocks.

Inventors

Jung Shik JANG

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260512
Application Date: 20231130
Priority Date: 20200914

Claims (10)

1 . A semiconductor memory device comprising: a stacked structure including a first plurality of insulation layers alternately stacked with a plurality of conductive layers; one or more slits configured to separate the stacked structure into a pair of memory stacks, the one or more slits extending along a first direction, and the pair of memory stacks being arranged along a second direction perpendicular to the first direction; and at least one bridge including a plurality of insulation layers, the at least one bridge configured to be arranged at the slits between slits, wherein the at least one bridge includes n insulating layers that are sequentially stacked, the n insulating layers extend from the plurality of the first insulation layers of the pair of memory stacks, wherein n is an integer equal to or greater than two, and wherein the n insulating layers are separate and distinct in a third direction perpendicular to both the first and second directions.
2 . The semiconductor memory device of claim 1 , further comprising a plurality of channel contacts formed in each of the pair of memory stacks.
3 . The semiconductor memory device of claim 1 , wherein the at least one bridge comprises a lower region and an upper region, and wherein the n insulating layers are located in at least one of the lower region and the upper region.
4 . The semiconductor memory device of claim 1 , wherein the at least one bridge further comprises a space provided between adjacent insulating layers among the n insulating layers that are sequentially stacked.
5 . A semiconductor memory device comprising: a stacked structure including a plurality of first insulation layers alternately stacked with a plurality of conductive layers; a plurality of slits configured to separate the stacked structure into a plurality of memory stacks arranged in parallel, the slits extending in parallel along a first direction, wherein the plurality of memory stacks are arranged along a second direction perpendicular to the first direction; and a plurality of insulation bridges configured to be arranged in the plurality of slits, and located between adjacent memory stacks in the second direction; and wherein the slits are positioned on both sides of each of the insulation bridges in the first direction, wherein at least one of the plurality of insulation bridges includes n insulating layers that are sequentially stacked, and the n insulating layers extend from the plurality of the first insulation layers of the plurality of memory stacks, wherein n is an integer equal to or greater than two, and wherein the n insulating layers are separate and distinct in a third direction perpendicular to both the first and second directions.
6 . The semiconductor memory device of claim 5 , wherein each of the plurality of insulation bridges includes a space provided between adjacent insulating layers among the n insulating layer that are sequentially stacked.
7 . The semiconductor memory device of claim 5 , wherein the plurality of insulation bridges are arranged having various sizes and arranged at various intervals between adjacent insulation bridges along the first direction.
8 . The semiconductor memory device of claim 5 , wherein each of the plurality of the memory stacks comprises a plurality of channel contacts formed in each of the memory stacks.
9 . The semiconductor memory device of claim 5 , wherein each of the memory stacks comprises a memory block.
10 . The semiconductor memory device of claim 5 , wherein each of the plurality of memory stacks includes a lower region and an upper region, and the n insulating layers extend from the plurality of first insulating layers located in the lower region of each of the plurality of memory stacks.

Description

CROSS-REFERENCES TO RELATED APPLICATION The present application is a continuation application of U.S. patent application Ser. No. 17/160,105, filed on Jan. 27, 2021 claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2020-0117386, filed on Sep. 14, 2020, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. BACKGROUND 1. Technical Field Various embodiments may generally relate to a semiconductor memory device and a method of manufacturing the same, more particularly to a semiconductor memory device including a plurality of memory blocks and a method of manufacturing the semiconductor memory device. 2. Related Art In order to meet needs of customers such as good performance, low price, etc., it may be required to increase an integration degree of a semiconductor memory device. Because the integration degree of the semiconductor memory device may be an important factor for determining the price of the semiconductor memory device, the increased integration degree may be necessary. In a conventional two-dimensional or planar semiconductor memory device, the integration degree may be determined by an area of a unit memory cell so that the integration degree may be greatly influenced by a technology for forming a fine pattern. However, expensive equipment may be required to form the fine pattern. Thus, although the integration degree of the two-dimensional semiconductor memory device may be increased, the integration degree may still be restricted. In order to overcome the restriction, three-dimensional semiconductor memory devices including three-dimensionally arranged memory cells may be proposed. The three-dimensional semiconductor device may include stacked memory cells. Thus, an integration density of the memory cell may closely relate to a height of a structure so that an aspect ratio may be increased due to the high integration density. SUMMARY In example embodiments of the present disclosure, a semiconductor memory device may include a plurality of memory blocks and an insulation bridge. The plurality of the memory blocks may be defined by a plurality of slits parallel to each other. The insulation bridge may be formed in the slits at both sides of the memory block to support adjacent memory blocks. In example embodiments of the present disclosure, a semiconductor memory device may include a plurality of memory blocks and at least one bridge. Each of the memory blocks may include a stacked structure. The stacked structure may include an insulation layer and a conductive layer alternately stacked. The at least one bridge may include the insulation layers of the memory block. The at least one bridge may be positioned between the adjacent memory blocks. In example embodiments, the bridges positioned at both sides of one memory block may correspond to each other. Alternatively, the bridges positioned at both sides of one memory block may not be facing each other. In example embodiments, numbers of the bridges at spaces between the memory blocks, i.e., the slits may be equal to or different from each other for each slit. In example embodiments of the present disclosure, a method of manufacturing a semiconductor memory device may include alternately stacking a first insulation layer and a second insulation layer to form a stacked structure. Slits may be formed at the stacked structure to divide the stack structure into a plurality of memory blocks. A preliminary bridge may be simultaneously formed in each of the slits to partially connect memory blocks of the stacked structure with each other. The second insulation layer of the preliminary bridge exposed through the slit may be selectively removed to form a space. A conductive layer for a word line may be formed in the space of the memory block and the preliminary bridge. The conductive layer for the word line remaining in the space of the preliminary bridge may be removed to form an insulation bridge. Removing the conductive layer for the word line remaining in the space of the preliminary bridge comprises simultaneously performing a process for removing the conductive layer for the word line remaining on a sidewall and a bottom surface of the slit. In an example embodiments, removing the conductive layer for the word line remaining on the sidewall and the bottom surface of the slit comprises over-etching the conductive layer for the word line remaining on the sidewall of the slit by a width (thickness) greater than a width of the conductive layer for the word line. A width of the insulation bridge is determined in accordance with an over-etched amount of the conductive layer for the word line remaining on the sidewall of the slit. A width of the insulation bridge is no more than two times the width of the over-etched conductive layer for the word line in the preliminary bridge or the width of the conductive layer for the word line remaining on the sidewall of the slit. In example embodiment