US-12628347-B2 - Memory structure with reduced read disturb

US12628347B2US 12628347 B2US12628347 B2US 12628347B2US-12628347-B2

Abstract

A memory structure including a memory array is provided. The memory array is a block including six sub-blocks. The memory array includes string select line portions and ground select line portions. The string select line portions are arranged along a first direction. Each of the string select line portions is located in the corresponding sub-block. The ground select line portions are arranged along the first direction. Each of the ground select line portions is shared by only two corresponding sub-blocks. The memory structure may be a 3D NAND flash memory with high capacity and high performance.

Inventors

Chi Sheng Peng
Ya Chun Tsai

Assignees

MACRONIX INTERNATIONAL CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20230927

Claims (15)

1 . A memory structure, comprising: a memory array, wherein the memory array is a block comprising six sub-blocks and comprises: string select line portions arranged along a first direction, wherein each of the string select line portions is located in the corresponding sub-block; ground select line portions arranged along the first direction, wherein each of the ground select line portions is shared by only two corresponding sub-blocks; and a first source line slit, a second source line slit, and a third source line slit sequentially arranged along the first direction and extending along a second direction, wherein the first direction intersects the second direction, the six sub-blocks comprise a first sub-block, a second sub-block, a third sub-block, a fourth sub-block, a fifth sub-block, and a sixth sub-block sequentially arranged along the first direction, the first sub-block, the second sub-block, and the third sub-block are located between the first source line slit and the second source line slit, the fourth sub-block, the fifth sub-block, and the sixth sub-block are located between the second source line slit and the third source line slit, and the second source line slit has an opening.
2 . The memory structure according to claim 1 , wherein each of the string select line portions comprises at least one string select line.
3 . The memory structure according to claim 1 , wherein each of the ground select line portions comprises at least one ground select line.
4 . The memory structure according to claim 1 , wherein the memory array comprises: a substrate; and a stack structure located on the substrate and comprising insulating layers and conductive layers alternately stacked.
5 . The memory structure according to claim 4 , wherein the ground select line portions are located between the string select line portions and the substrate.
6 . The memory structure according to claim 4 , wherein each of the string select line portions comprises at least one of the conductive layers in a upper portion of the stack structure, the conductive layers in a middle portion of the stack structure are used as word lines, and each of the ground select line portions comprises at least one of the conductive layers in a lower portion of the stack structure.
7 . The memory structure according to claim 6 , wherein the memory array further comprises: channel pillars located in the stack structure.
8 . The memory structure according to claim 7 , wherein the memory array further comprises: charge storage structures located between the channel pillars and the word lines.
9 . The memory structure according to claim 1 , wherein the ground select line portions comprise a first ground select line portion, a second ground select line portion, and a third ground select line portion sequentially arranged along the first direction, the first ground select line portion is shared by the first sub-block and the second sub-block, the second ground select line portion is shared by the third sub-block and the fourth sub-block, and the third ground select line portion is shared by the fifth sub-block and the sixth sub-block.
10 . The memory structure according to claim 9 , wherein the memory array further comprises: a first isolation slit and a second isolation slit sequentially arranged along the first direction and extending along the second direction, wherein the first isolation slit is located between the first source line slit and the second source line slit, and the second isolation slit is located between the second source line slit and the third source line slit.
11 . The memory structure according to claim 10 , wherein the first ground select line portion is located between the first source line slit and the first isolation slit, the second ground select line portion is located between the first isolation slit and the second isolation slit, and the third ground select line portion is located between the second isolation slit and the third source line slit.
12 . The memory structure according to claim 10 , wherein the memory array further comprises: a third isolation slit, a fourth isolation slit, a fifth isolation slit, and a sixth isolation slit sequentially arranged along the first direction and extending along the second direction, wherein the first sub-block is located between the first source line slit and the third isolation slit, the second sub-block is located between the third isolation slit and the fourth isolation slit, the third sub-block is located between the fourth isolation slit and the second source line slit, the fourth sub-block is located between the second source line slit and the fifth isolation slit, the fifth sub-block is located between the fifth isolation slit and the sixth isolation slit, and the sixth sub-block is located between the sixth isolation slit and the third source line slit.
13 . The memory structure according to claim 12 , wherein the third isolation slit, the fourth isolation slit, the fifth isolation slit, and the sixth isolation slit are located above the first isolation slit and the second isolation slit, the fourth isolation slit is aligned with the first isolation slit, and the fifth isolation slit is aligned with the second isolation slit.
14 . The memory structure according to claim 1 , wherein a ground select line in the first ground select line portion is integrally formed, a ground select line in the second ground select line portion is integrally formed, and a ground select line in the third ground select line portion is integrally formed.
15 . The memory structure according to claim 1 , wherein the memory array further comprises: a seventh isolation slit extending along the second direction, wherein the seventh isolation slit is located between the fourth isolation slit and the fifth isolation slit and is aligned with the second source line slit and the opening.

Description

BACKGROUND Technical Field The invention relates to a semiconductor structure, and particularly relates to a memory structure. Description of Related Art Since a non-volatile memory device (e.g., flash memory) has the advantage that stored data does not disappear at power-off, it becomes a widely used memory device for a personal computer or other electronics equipment. Currently, the flash memory array commonly used in the industry includes a NOR flash memory and a NAND flash memory. Since the NAND flash memory has a structure in which memory cells are connected together in series, degree of integration and area utilization thereof are better than those of the NOR flash memory. Thus, the NAND flash memory has been widely used in a variety of electronic products. Besides, to further enhance the degree of integration of the memory device, a three-dimensional (3D) NAND flash memory has been developed. However, there are still some challenges (e.g., read disturb) associated with the 3D NAND flash memory. SUMMARY The invention provides a memory structure, which can effectively reduce the read disturb. The invention provides a memory structure, which includes a memory array. The memory array is a block including six sub-blocks. The memory array includes string select line portions and ground select line portions. The string select line portions are arranged along a first direction. Each of the string select line portions is located in the corresponding sub-block. The ground select line portions are arranged along the first direction. Each of the ground select line portions is shared by only two corresponding sub-blocks. According to an embodiment of the invention, in the memory structure, each of the string select line portions may include at least one string select line. According to an embodiment of the invention, in the memory structure, each of the ground select line portions may include at least one ground select line. According to an embodiment of the invention, in the memory structure, the memory array may include a substrate and a stack structure. The stack structure is located on the substrate. The stack structure includes insulating layers and conductive layers alternately stacked. According to an embodiment of the invention, in the memory structure, the ground select line positions may be located between the string select line portions and the substrate. According to an embodiment of the invention, in the memory structure, each of the string select line portions may include at least one of the conductive layers in the upper portion of the stack structure. The conductive layers in the middle portion of the stack structure may be used as word lines. Each of the ground select line portions may include at least one of the conductive layers in the lower portion of the stack structure. According to an embodiment of the invention, in the memory structure, the memory array may further include channel pillars. The channel pillars are located in the stack structure. According to an embodiment of the invention, in the memory structure, the memory array may further include charge storage structures. The charge storage structures are located between the channel pillars and the word lines. According to an embodiment of the invention, in the memory structure, the memory array may further include a first source line slit, a second source line slit, and a third source line slit. The first source line slit, the second source line slit, and the third source line slit may be sequentially arranged along the first direction and may extend along a second direction. The first direction may intersect the second direction. According to an embodiment of the invention, in the memory structure, the six sub-blocks may include a first sub-block, a second sub-block, a third sub-block, a fourth sub-block, a fifth sub-block, and a sixth sub-block sequentially arranged along the first direction. The first sub-block, the second sub-block, and the third sub-block may be located between the first source line slit and the second source line slit. The fourth sub-block, the fifth sub-block, and the sixth sub-block may be located between the second source line slit and the third source line slit. According to an embodiment of the invention, in the memory structure, the ground select line portions may include a first ground select line portion, a second ground select line portion, and a third ground select line portion sequentially arranged along the first direction. The first ground select line portion may be shared by the first sub-block and the second sub-block. The second ground select line portion may be shared by the third sub-block and the fourth sub-block. The third ground select line portion may be shared by the fifth sub-block and the sixth sub-block. According to an embodiment of the invention, in the memory structure, the memory array may further include a first isolation slit and a second isolation slit. The first isolation slit a