US-12628348-B2 - Three-dimensional flash memory having improved integration density

Abstract

The present invention relates to a three-dimension flash memory to which an efficient word line connection structure is applied, and a method for manufacturing same, wherein a plurality of word lines are connected to a low decoder respectively through contacts of the plurality of word lines, a plurality of connection wires, and plug vias of the plurality of word lines. The row decoder and a column decoder are arranged to divide a plurality of peripheral circuit blocks such that the plurality of peripheral circuit blocks are symmetrical to each other in the plane of the three-dimensional flash memory. The three-dimension flash memory is configured in a buried type in which a common source line is buried in a substrate, in order to improve integration density.

Inventors

• Yun Heub Song
• Inho Nam

Assignees

• IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)

Dates

Publication Date

20260512

Application Date

20210705

Priority Date

20200724

Claims (9)

1. 1 . A three-dimensional flash memory to which an efficient word line connection structure is applied, the three-dimensional flash memory comprising: at least one memory cell string extending in one direction; a plurality of word lines vertically connected to the at least one memory cell string; and a row decoder located below the plurality of word lines, wherein each of the plurality of word lines is connected to the row decoder through a plug via connected to a contact of each of the plurality of word lines, wherein a plurality of connection wires connecting the plug via of each of the plurality of word lines to the contact of each of the plurality of word lines are arranged in a plane of the plurality of word lines, wherein the plurality of connection wires include a vertical portion and a horizontal portion, and wherein, on the plane of the plurality of word lines, a position of each plug via and a position of each contact are configured to minimize a length of the horizontal portion of each of the plurality of connection wires.
2. 2 . The three-dimensional flash memory of claim 1 , wherein the plug via of each of the plurality of word lines passes through each of the plurality of word lines on a plane of the plurality of word lines and contacts the row decoder.
3. 3 . The three-dimensional flash memory of claim 2 , wherein the plug via of each of the plurality of word lines has a structure that is isolated from each of the plurality of word lines on the plane.
4. 4 . The three-dimensional flash memory of claim 3 , wherein the plug via of each of the plurality of word lines is isolated from each of the plurality of word lines on a plane by an oxide layer formed between the plurality of word lines.
5. 5 . A three-dimensional flash memory having a structure for efficient layout, the three-dimensional flash memory comprising: at least one cell block each including a plurality of memory cell strings extending on a substrate in one direction; a plurality of peripheral circuit blocks, each including at least one peripheral circuit and located below the at least one cell block as a cell on peripheral (COP) structure is applied; a row decoder for the at least one cell block and the plurality of peripheral circuit blocks; and a column decoder for the at least one cell block and the plurality of peripheral circuit blocks, wherein the row decoder and the column decoder are arranged while dividing the plurality of peripheral circuit blocks such that the plurality of peripheral circuit blocks are symmetrical to each other.
6. 6 . The three-dimensional flash memory of claim 5 , wherein the row decoder and the column decoder are arranged in a cross shape in a plane of the three-dimensional flash memory to symmetrically divide the plurality of peripheral circuit blocks into quadrants formed by the cross shape.
7. 7 . The three-dimensional flash memory of claim 6 , wherein the row decoder and the column decoder are arranged in the cross shape as the row decoder is located in a vertical direction and the column decoder is located in a horizontal direction across a midpoint of the row decoder in the plane of the 3D flash memory.
8. 8 . The three-dimensional flash memory of claim 5 , wherein the row decoder and the column decoder are arranged in a T-shape in a plane of the three-dimensional flash memory and symmetrically divide the plurality of peripheral circuit blocks into two quadrants formed by the T-shape.
9. 9 . The three-dimensional flash memory of claim 8 , wherein the row decoder and the column decoder are arranged in the T-shape as the column decoder is located in a horizontal direction and the row decoder is located in a vertical direction from a midpoint of the column decoder to one point in the plane of the three-dimensional flash memory.

Description

TECHNICAL FIELD The following embodiments relate to a three-dimensional (3D) flash memory, and more particularly, to a technology for a 3D flash memory having improved integration. BACKGROUND ART Flash memory is an electrically erasable programmable read-only memory (EEPROM), which electrically controls inputs and outputs of data by Fowler-Nordheim tunneling or hot electron injection. Recently, a three-dimensional (3D) structure is applied to a flash memory in which the degree of integration is increased by increasing the length of a memory cell string in a vertical direction in order to satisfy excellent performance and low price required by consumers. Referring to FIG. 1 illustrating such a conventional 3D flash memory, a 3D flash memory 100 has a structure that includes a channel layer 120 formed on a substrate 110 in a vertical direction, a charge storage layer 130 formed to surround the channel layer 120, a plurality of word lines 140 connected to the charge storage layer 130 and stacked in a horizontal direction, and a plurality of insulation layers 150 alternately interposed between the plurality of word lines 140. Hereinafter, the charge storage layer 130, the channel layer 120 and the plurality of word lines 140, which are components directly related to data storage and reading, may constitute a memory cell string. Such a conventional 3D flash memory 100 may further include a row decoder 160 disposed below the plurality of word lines 140 to perform a selection operation on the plurality of word lines 140. In the 3D flash memory 100 having such a structure, each of the plurality of word lines 140 is connected to the row decoder 160 through an outer wire 161 connected to a contact 141 of each of the plurality of word lines 140. Accordingly, because the outer wire 161 has a connection path that is out of plane of the plurality of word lines 140, the conventional 3D flash memory 100 may have a delayed operation speed, a low degree of integration, and a complicated layout structure. Therefore, there is a need to propose a technique for solving the problems of the existing 3D flash memory 100. Recently, a cell on peripheral (COP) structure in which at least one peripheral circuit is disposed on a substrate is applied to a flash memory. Because the wire complexity of at least one peripheral circuit is increased due to such a structure, it is required to effectively lay out at least one peripheral circuit together with a row decoder and a column decoder. Therefore, the following embodiments propose a 3D flash memory to which a structure for efficient layout is applied. Referring to FIGS. 15A and 15B showing a conventional 3D flash memory, a 3D flash memory 1500 has a structure which includes a plurality of memory cell strings 120 including a channel layer 1521 extending from the substrate 1510 in one direction (e.g., Z direction which is a vertical direction) and a charge storage layer 1522 formed to surround the channel layer 1521, a plurality of word lines 1530 connected in a direction perpendicular to the plurality of memory cell strings 1520, and a common source line 1540 extending upwardly of the substrate 1510 as high as the plurality of memory cell strings 1520 to have a step difference. In this case, as well as a function of a source electrode for the plurality of memory cell strings 1520, the common source line 1540 has a function of separating the plurality of word lines 1530 for each of the plurality of memory blocks 1521 and 1522 in which the plurality of memory cell strings 1520 are grouped in an arbitrary number, and a function of separating a string selection line (SSL) 1531 located on upper ends of the plurality of word lines 1530 in the plurality of memory blocks 1521 and 1522. Meanwhile, because the common source line 1540 is formed to have a step difference on the substrate 1510 as described above, the conventional 3D flash memory has a high complexity of a source line manufacturing process and low cell integration. Therefore, there is a need to propose a technique to solve the disadvantages of a conventional 3D flash memory by changing the structure of a source line while guaranteeing the functions of a common source line. DETAILED DESCRIPTION OF THE INVENTION Technical Problem Embodiments of the present disclosure propose a 3D flash memory having a structure that is capable of minimizing the length of a connection path by arranging the connection path from a plurality of word lines to a row decoder in a plane of the plurality of word lines in order to prevent operation speed delay, improve integration and have a simple layout structure. More specifically, embodiments of the present disclosure propose a 3D flash memory having a structure in which each of the plurality of word lines is connected to a row decoder through a contact of each of the plurality of word lines, a plurality of connection wires, and a plug via of each of the plurality of word lines. Embodiments of the present discl