US-12628349-B2 - Protection of channel layer in three-terminal vertical memory structure

US12628349B2US 12628349 B2US12628349 B2US 12628349B2US-12628349-B2

Abstract

Channel material is conformally deposited along sidewalls of one or more etched features of a mold stack in fabricating a three-terminal memory device. The channel material is deposited in recessed regions and non-recessed regions of the one or more etched features. A sacrificial liner is deposited on the channel material. A directional etch removes the sacrificial liner from non-recessed regions of the one or more etched features. An isotropic etch removes the channel material from non-recessed regions of the one or more etched features, leaving the channel material and the sacrificial liner intact in the recessed regions. The sacrificial liner is removed, leaving the channel material intact and isolated with minimal loss of channel material from over-etch.

Inventors

John Hoang
Meihua Shen
Thorsten Bernd Lill
Hui-Jung Wu
Aaron Lynn Routzahn
Francis Sloan Roberts

Assignees

LAM RESEARCH CORPORATION

Dates

Publication Date: 20260512
Application Date: 20210301

Claims (13)

1 . A method of forming an isolated channel layer comprising: (i) etching one or more features through a mold stack, the mold stack comprising a plurality of film stacks, wherein the plurality of film stacks is vertically stacked and adjacent film stacks are separated by a dielectric layer, each film stack comprising: a source region, a drain region, and an oxide layer between the source region and the drain region; (ii) selectively etching at least a portion of the oxide layer in each of the film stacks to form a recessed region in each of the film stacks; (iii) depositing a channel material conformally along sidewalls of the one or more features; (iv) depositing a sacrificial liner covering the channel material along the sidewalls of the one or more features; (v etching the sacrificial liner covering the channel material in areas outside the recessed region; (vi) selectively etching at least the channel material along the sidewalls of the one or more features outside the recessed region to define an isolated channel layer between the source region and the drain region of each film stack; and (vii) removing, after selectively etching at least the channel material outside the recessed region, an entirety of the sacrificial liner overlying the isolated channel layer.
2 . The method of claim 1 , wherein the isolated channel layer has topographical deviations no greater than about 10% from a reference surface after removing the sacrificial liner.
3 . The method of claim 1 , wherein each film stack further comprises a conductor layer adjacent to the drain region and sandwiched between the drain region and the dielectric layer, wherein the dielectric layer serves to electrically isolate the adjacent film stacks from one another.
4 . The method of claim 1 , wherein etching the sacrificial liner in the areas outside the recessed region comprises directionally etching the sacrificial liner at an etch contrast of at least 10:1 relative to the channel material.
5 . The method of claim 4 , wherein protrusions from the sidewalls of the one or more features serve as a mask to protect the recessed region during the directional etching of the sacrificial liner.
6 . The method of claim 1 , wherein selectively etching at least the channel material in the areas outside the recessed region comprises isotropically etching the channel material at an etch contrast of at least 25:1 relative to the sacrificial liner.
7 . The method of claim 6 , wherein isotropically etching the channel material occurs at an etch contrast of at least 10:1 relative to at least the dielectric layer.
8 . The method of claim 1 , wherein the channel material comprises a semiconducting material, and wherein the sacrificial liner comprises a bilayer of a carbide and oxide material.
9 . The method of claim 8 , wherein the semiconducting material comprises polysilicon, and wherein the sacrificial liner comprises a first layer of oxide disposed on the semiconducting material and a second layer of carbide disposed on the first layer of oxide.
10 . The method of claim 1 , wherein the sacrificial liner is conformally deposited on the channel material along the sidewalls of the one or more features.
11 . The method of claim 1 , wherein the plurality of film stacks comprises greater than 20 repeating film stacks.
12 . The method of claim 1 , wherein the sidewalls of the one or more features in the areas outside the recessed region are substantially free of channel material after selectively etching at least the channel material.
13 . The method of claim 1 , wherein an average thickness of the isolated channel layer is between about 5 nm and about 20 nm.

Description

INCORPORATION BY REFERENCE A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in its entirety and for all purposes. BACKGROUND Advances in semiconductor device fabrication have led to an increased number of memory devices on a chip. Not only have advancements been made to scale to smaller and smaller features for greater density, but advancements have been made to arrange memory devices from two-dimensional (2-D) architectures to three-dimensional (3-D) architectures. In 2-D memories, memory cells are arranged side by side on a single die layer. In 3-D memories, more planes of memory cells can stack over one another in a given footprint on limited die size, which can lead to increased capacity and performance. The background provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent that it is described in this background, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. SUMMARY Certain embodiments herein relate to a method of forming an isolated channel layer for a vertically integrated memory array. The method includes: (i) etching one or more features through a mold stack, where the mold stack is disposed on a semiconductor substrate, the mold stack comprising a plurality of film stacks, where the plurality of film stacks is vertically stacked and adjacent film stacks are separated by a dielectric layer, each film stack comprising: a source region, a drain region, and an oxide layer between the source region and the drain region. The method further includes (ii) selectively etching at least a portion of the oxide layer in each of the film stacks to form a recessed region in each of the film stacks, (iii) depositing a channel material conformally along sidewalls of the one or more features, (iv) depositing a sacrificial liner covering the channel material along the sidewalls of the one or more features, (v) etching the sacrificial liner covering the channel material in areas outside the recessed region, and (vi) selectively etching at least the channel material along the sidewalls of the one or more features outside the recessed region to define an isolated channel layer between the source region and the drain region of each film stack. In some implementations, the method further includes (vii) removing, after selectively etching at least the channel material outside the recessed region, the sacrificial liner overlying the isolated channel layer. In some implementations, the isolated channel layer has topographical deviations no greater than about 10% from a reference surface after removing the sacrificial liner. In some implementations, each film stack further comprises a conductor layer adjacent to the drain region and sandwiched between the drain region and the dielectric layer, where the dielectric layer serves to electrically isolate the adjacent film stacks from one another. In some implementations, etching the sacrificial liner in the areas outside the recessed region comprises directionally etching the sacrificial liner at an etch contrast of at least 10:1 relative to the channel material. In some implementations, protrusions from the sidewalls of the one or more features serve as a mask to protect the recessed region during the directional etching of the sacrificial liner. In some implementations, selectively etching at least the channel material in the areas outside the recessed region comprises isotropically etching the channel material at an etch contrast of at least 25:1 relative to the sacrificial liner. In some implementations, isotropically etching the channel material occurs at an etch contrast of at least 10:1 relative to at least the dielectric layer. In some implementations, the sacrificial liner is conformally deposited on the channel material along the sidewalls of the one or more features. Another aspect of the disclosed embodiments relates to a memory device. The memory device includes (i) a plurality of three-terminal memory cells, each memory cell comprising: a source terminal connected to a source region, a drain terminal connected to a drain region, an oxide layer between the source region and the drain region, an isolated channel layer on a surface of the oxide layer and providing interconnection between the source region and the drain region, a gate terminal, and a memory film between the isolated channel layer and the gate terminal. The memory device further includes (ii) a plurality of dielectric layers each separating adjacent three-terminal memory cells, where the plurality of three-terminal memory cells is vertically stacked.