US-12628350-B2 - Manganese or scandium doped ferroelectric device and bit-cell

US12628350B2US 12628350 B2US12628350 B2US 12628350B2US-12628350-B2

Abstract

Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

Inventors

Sasikanth Manipatruni
Rajeev Kumar Dokania
Ramamoorthy Ramesh

Assignees

Kepler Computing Inc.

Dates

Publication Date: 20260512
Application Date: 20221019

Claims (7)

1 . An apparatus comprising: a transistor having a source, a drain, and a gate; a word-line coupled to the gate; a bit-line coupled to one of the source or drain of the transistor; a plate-line; and a capacitive structure coupled to one of the source or drain of the transistor through one or more vias, and to the plate-line, wherein the capacitive structure comprises: a first ferroelectric material having a first inverted u-shape; a second ferroelectric material having a second inverted u-shape, wherein the first ferroelectric material and the second ferroelectric material include Mn or Sc dopants to control leakage through the first ferroelectric material and the second ferroelectric material; a first conductive oxide inside a first gap area of the first inverted u-shape, wherein the first conductive oxide abuts inner sidewalls of the first ferroelectric material, and wherein the first conductive oxide fully fills the first gap area; a second conductive oxide inside a second gap area of the second inverted u-shape, wherein the second conductive oxide abuts inner sidewalls of the second ferroelectric material, and wherein the second conductive oxide fully fills the second gap area; a third conductive oxide between a first outer sidewall of the first ferroelectric material and a first outer sidewall of the second ferroelectric material; an electrode that abuts the first ferroelectric material and the second ferroelectric material such that the electrode abuts bottom surfaces of the first inverted u-shape of the first ferroelectric material and of the second inverted u-shape of the second ferroelectric material, wherein the electrode couples to the source or the drain of the transistor; a fourth conductive oxide that buts a second outer sidewall of the first ferroelectric material; a fifth conductive oxide that buts a second outer sidewall of the second ferroelectric material; and a sixth conductive oxide that buts upper surfaces of the first inverted u-shape of the first ferroelectric material and of the second inverted u-shape of the second ferroelectric material, wherein the sixth conductive oxide abuts portions of the third conductive oxide, the fourth conductive oxide, and the fifth conductive oxide.
2 . The apparatus of claim 1 , wherein the electrode comprises a refractive inter-metallic material, and wherein the electrode comprises metal.
3 . The apparatus of claim 1 , wherein the electrode is a first electrode, wherein the apparatus comprises a second electrode, and wherein the second electrode abuts the sixth conductive oxide.
4 . The apparatus of claim 3 , wherein the plate-line abuts the second electrode.
5 . The apparatus of claim 3 , wherein the capacitive structure comprises an insulative material that abuts outer sidewall of the fourth conductive oxide and the outer sidewall of the fifth conductive oxide.
6 . The apparatus of claim 5 , wherein the insulative material comprises an oxide of Al.
7 . The apparatus of claim 6 , wherein the insulative material further comprises Ti.

Description

CLAIM OF PRIORITY This application is a continuation of, and claims the benefit of priority to U.S. patent application Ser. No. 17/820,865, filed Aug. 18, 2022, and now issued as U.S. Pat. No. 12,457,752 on Oct. 28, 2025, which is a Continuation of, and claims the benefit of priority to U.S. patent application Ser. No. 16/287,953, filed Feb. 27, 2019, titled “HIGH-DENSITY LOW VOLTAGE NON-VOLATILE MEMORY WITH UNIDIRECTIONAL PLATE-LINE AND BIT-LINE AND PILLAR CAPACITOR,” now issued as U.S. Pat. No. 11,476,260 on Oct. 18, 2022, and which is incorporated by reference in its entirety. BACKGROUND The standard memory used in processors is static random-access memory (SRAM) or dynamic random access memory (DRAM), and their derivatives. These memories are volatile memories. For example, when power to the memories is turned off, the memories lose their stored data. Non-volatile memories are now also commonly used in computing platforms to replace magnetic hard disks. Non-volatile memories retain their stored data for prolonged periods (e.g., months, years, or forever) even when power to those memories is turned off. Examples of non-volatile memories are magnetic random-access memory (MRAM), NAND or NOR flash memories. These memories may not be suitable for low power and compact computing devices because these memories suffer from high write energy, low density, and high power consumption. The background description provided here is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated here, the material described in this section is not prior art to the claims in this application and are not admitted as prior art by inclusion in this section. BRIEF DESCRIPTION OF THE DRAWINGS The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only. FIGS. 1A-B illustrate a three-dimensional (3D) view and corresponding cross-section, respectively, of 1T-1C (one planar transistor and one capacitor) memory bit-cell comprising a pillar capacitor having ferroelectric material and conductive oxides as electrodes, wherein one of the conductive oxide electrodes wraps around the pillar capacitor, in accordance with some embodiments. FIG. 1C illustrates a cross-section of a 1T-1C memory bit-cell wherein the pillar capacitor having FE material is formed between plate-line (PL) and bit-line (BL), in accordance with some embodiments. FIG. 1D illustrates a cross-section of a 1T-1C memory bit-cell wherein two pillar capacitors having FE material are formed between plate-line (PL) and bit-line (BL), in accordance with some embodiments. FIG. 2 illustrates a high-density layout of the 1T-1C bit-cell of FIG. 1, in accordance with some embodiments. FIGS. 3A-B illustrate a 3D view of pillar capacitors, respectively, with side wall-barrier seal, in accordance with some embodiments. FIG. 4A illustrates a 3D view of a pillar capacitor with wrap-around conductive oxide as a first electrode over a ferroelectric structure, and refractive inter-metallic inside the pillar as a second electrode, in accordance with some embodiments. FIG. 4B illustrates a 3D view of pillar capacitor with wrap-around conductive oxide as a first electrode over a ferroelectric structure, and a stack of refractive inter-metallic inside the pillar as a second electrode, wherein the stack has a metal coating, in accordance with some embodiments. FIGS. 5A-B illustrate a 3D view and corresponding cross-section, respectively, of 1T-1C (one finFET and one capacitor) memory bit-cell comprising a pillar capacitor having ferroelectric material and conductive oxides as electrodes, wherein one of the conductive oxide electrodes wraps around the pillar capacitor, in accordance with some embodiments. FIG. 6 illustrates a high-density layout of the 1T-1C bit-cell of FIG. 5A, in accordance with some embodiments. FIG. 7 illustrates a 3D view of 1T-1C (one backend finFET and one capacitor) memory bit-cell comprising a pillar capacitor having ferroelectric material and conductive oxides as electrodes, wherein one of the conductive oxide electrode wraps around the pillar capacitor, in accordance with some embodiments. FIG. 8 illustrates a flowchart for forming a 1T-1C bit-cell, in accordance with some embodiments. FIG. 9 illustrates a flowchart for forming the pillar capacitor for the 1T-1C bit-cell, in accordance with some embodiments. FIG. 10 illustrates a memory chip having an array of 1T-1C bit-cells and logic, in accordance with some embodiments. DETAILED DESCRIPTION Some embodiments describe a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material and conductive oxides as electrodes. In various embodiments, one layer