US-12628351-B2 - Memory cell and memory cell array

US12628351B2US 12628351 B2US12628351 B2US 12628351B2US-12628351-B2

Abstract

A memory cell array of the present disclosure includes a plurality of memory cells 11 arranged in a first direction and a second direction different from the first direction. Each of the memory cells 11 includes a resistance-variable nonvolatile memory element and a selection transistor TR electrically connected to the nonvolatile memory element. The selection transistor TR is formed in an active region 80 provided in a semiconductor layer 60 . At least a part of the active region 80 is in contact with an element isolation region 81 provided in the semiconductor layer 60 . A surface of the element isolation region 81 is located at a position lower than a surface of the active region 80.

Inventors

Mikio Oka
Kazuki Yamaguchi
Masashi KINO
Takashige Doi
Masashige Moritoki
Takashi Watanabe
Norikazu Kasahara

Assignees

SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Dates

Publication Date: 20260512
Application Date: 20210129
Priority Date: 20200303

Claims (17)

1 . A memory cell array comprising a plurality of memory cells arranged in a first direction and a second direction different from the first direction, wherein each of the memory cells includes: a resistance-variable nonvolatile memory element; and a selection transistor electrically connected to the nonvolatile memory element, the selection transistor is formed in an active region provided in a semiconductor layer, at least a part of the active region is in contact with an element isolation region provided in the semiconductor layer, a surface of the element isolation region is located at a position lower than a surface of the active region, the memory cells adjacent to each other in the second direction are isolated from each other by the element isolation region, and the memory cells adjacent to each other in the first direction are isolated from each other by an element isolation transistor.
2 . The memory cell array according to claim 1 , wherein a first one of the nonvolatile memory element constituting a (2m−1)-th (in which m=1, 2, 3 . . . ) memory cell arranged in the first direction is arranged on a first-A virtual line extending in the first direction, and a second one of the nonvolatile memory element constituting a 2m-th memory cell is arranged on a first-B virtual line extending in the first direction and located away from the first-A virtual line in the second direction.
3 . The memory cell array according to claim 1 , wherein a difference in a height direction between a top surface of the active region and a surface of the element isolation region is 15 nm to 35 nm.
4 . The memory cell array according to claim 1 , wherein the selection transistor includes a gate electrode, a gate insulating layer, a channel forming region, and source/drain regions, one source/drain region of the selection transistor is electrically connected to one end of the nonvolatile memory element, the other source/drain region of the selection transistor is electrically connected to a first wire, the other end of the nonvolatile memory element is electrically connected to a second wire, a word line also serving as the gate electrode of the selection transistor extends in the second direction, and the channel forming region and the source/drain regions of the selection transistor are arranged in the first direction.
5 . The memory cell array according to claim 4 , wherein the other source/drain region of the selection transistor is shared by a (2m−1)-th (in which m=1, 2, 3 . . . ) memory cell and a 2m-th memory cell arranged in the first direction, and the 2m-th memory cell and a (2m+1)-th memory cell are isolated from each other by an element isolation transistor.
6 . The memory cell array according to claim 4 , wherein the word line of the selection transistor extends from an edge portion of the active region along a side surface of the active region in the second direction, and further extends on the element isolation region.
7 . The memory cell array according to claim 4 , wherein when a difference in a height direction between a top surface of the active region and a surface of the element isolation region is represented by ΔH, and a width of the channel forming region of the selection transistor in the second direction is represented by L w , 0.08≤ΔH/L w ≤0.28 is satisfied.
8 . The memory cell array according to claim 1 , wherein the element isolation region has a shallow trench structure.
9 . The memory cell array according to claim 1 , wherein an end portion of the active region facing the element isolation region is rounded.
10 . A memory cell array comprising a plurality of memory cells arranged in a first direction and a second direction different from the first direction, wherein each of the memory cells includes: a resistance-variable nonvolatile memory element; and a selection transistor electrically connected to the nonvolatile memory element, a first one of the nonvolatile memory element constituting a (2m−1)-th (in which m=1, 2, 3 . . . ) memory cell arranged in the first direction is arranged on a first-A virtual line extending in the first direction, and a second one of the nonvolatile memory element constituting a 2m-th memory cell is arranged on a first-B virtual line extending in the first direction and located away from the first-A virtual line in the second direction, the selection transistor includes a gate electrode, a gate insulating layer, a channel forming region, and source/drain regions, one source/drain region of the selection transistor is electrically connected to one end of the nonvolatile memory element, the other source/drain region of the selection transistor is electrically connected to a first wire, the other end of the nonvolatile memory element is electrically connected to a second wire, a word line also serving as the gate electrode of the selection transistor extends in the second direction, the channel forming region and the source/drain regions of the selection transistor are arranged in the first direction, the other source/drain region of the selection transistor is shared by a (2m−1)-th memory cell and a 2m-th memory cell, and the 2m-th memory cell and a (2m+1)-th memory cell are isolated from each other by an element isolation transistor.
11 . The memory cell array according to claim 10 , wherein the memory cells adjacent to each other in the second direction are isolated from each other by an element isolation region.
12 . The memory cell array according to claim 10 , wherein the memory cells adjacent to each other in the first direction are isolated from each other by an element isolation transistor.
13 . The memory cell array according to claim 10 , wherein the other source/drain region of a first element isolation transistor also serves as one source/drain region of the selection transistor in the (2m−1)-th memory cell, and one source/drain region of a second element isolation transistor also serves as one source/drain region of the selection transistor in the 2m-th memory cell.
14 . The memory cell array according to claim 10 , wherein a nonvolatile memory element of a (2m−1)-th memory cell and a nonvolatile memory element of a 2m-th memory cell arranged in the first direction are arranged two-fold rotationally symmetrically with the selection transistor as a rotation axis.
15 . The memory cell array according to claim 10 , wherein when a distance in the first direction between a nonvolatile memory element of a (2m−1)-th memory cell and a nonvolatile memory element of a 2m-th memory cell arranged in the first direction is represented by LL 1 , and a distance in the first direction between the nonvolatile memory element of the 2m-th memory cell and a nonvolatile memory element of a (2m+1)-th memory cell arranged in the first direction is represented by LL 2 , LL 2 <LL 1 is satisfied.
16 . A memory cell comprising: a resistance-variable nonvolatile memory element; and a selection transistor electrically connected to the nonvolatile memory element, wherein the selection transistor is formed in an active region provided in a semiconductor layer, at least a part of the active region is in contact with an element isolation region provided in the semiconductor layer, a surface of the element isolation region is located at a position lower than a surface of the active region, and a word line of the selection transistor extends from an edge portion of the active region along a side surface of the active region in the second direction, and further extends on the element isolation region.
17 . A memory cell comprising: a resistance-variable nonvolatile memory element; and a selection transistor electrically connected to the nonvolatile memory element, wherein the selection transistor is formed in an active region provided in a semiconductor layer, at least a part of the active region is in contact with an element isolation region provided in the semiconductor layer, a surface of the element isolation region is located at a position lower than a surface of the active region, and when a difference in a height direction between a top surface of the active region and a surface of the element isolation region is represented by ΔH, and a width of a channel forming region of the selection transistor in the second direction is represented by L W , 0.08≤ΔH/L W ≤0.28 is satisfied.

Description

TECHNICAL FIELD The present disclosure relates to a memory cell and a memory cell array including the memory cell. BACKGROUND ART Along with rapid development of various information devices from a large-capacity server to a mobile terminal, further improvement in performance such as higher integration, higher speed, and lower power consumption has been pursued in various elements such as a memory and a logic constituting the information devices. In particular, a semiconductor nonvolatile memory has remarkably progressed, and for example, a flash memory as a large-capacity file memory is spreading at a speed of expelling a hard disk drive. Meanwhile, in view of development to a memory for code storage and a working memory, a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), a phase-change random access memory (PCRAM), and the like are being developed in order to replace a currently generally used NOR flash memory, DRAM, and the like with these memories, and some of these memories have already been put into practical use. Among these memories, the MRAM performs data storage (recording) on the basis of a magnetization direction of a magnetic body, and therefore can perform rewrite at high speed and almost infinitely (1015 times or more). The MRAM is already used in the fields of industrial automation, aircraft, and the like. In addition, the MRAM is expected to be developed to a memory for code storage and a working memory in the future due to its high-speed operation and high reliability. However, in reality, the MRAM has a problem in reducing power consumption and increasing capacity. This is an essential problem caused by a recording principle of the MRAM, that is, a system of reversing magnetization by a current magnetic field generated from a wire. As a means for solving this problem, a recording method that does not depend on a current magnetic field, that is, a magnetization reversal method has been studied. In particular, a spin transfer torque based magnetic random access memory (STT-MRAM) to which magnetization reversal by spin transfer is applied has attracted attention. Similarly to the MRAM, the spin transfer torque based magnetic random access memory (hereinafter, simply referred to as “nonvolatile memory element”) is constituted by, for example, magnetic tunnel junction (MTJ), and utilizes application of torque to a storage layer when a spin-polarized electron that has passed through a magnetic layer fixed in a certain direction enters another magnetic layer (a magnetic layer whose magnetization direction is not fixed, and is also referred to as a “free layer” or a “storage layer”). When a current (write current) equal to or larger than a certain threshold flows through the nonvolatile memory element, a magnetization direction of the storage layer is reversed. Data of “0/1” is rewritten by changing the polarity of the write current (a direction in which a current passing through the storage layer flows). In addition, an absolute value of the write is 1 mA or less in a nonvolatile memory element of a scale of about 0.1 μm, and a required write current value decreases in proportion to the volume of the nonvolatile memory element. Therefore, scaling can be performed. In addition, since a word line for generating a recording current magnetic field, which is required in the MRAM, is not required, there is also an advantage that a cell structure is simplified. Various materials have been studied as a ferromagnetic material used in a nonvolatile memory element. In general, a nonvolatile memory element having perpendicular magnetic anisotropy is considered to be more suitable for reducing power and increasing capacity than a nonvolatile memory element having in-plane magnetic anisotropy. This is because the perpendicular magnetization has a lower energy barrier to be exceeded at the time of spin torque magnetization reversal, and high magnetic anisotropy of a perpendicular magnetization film is advantageous for maintaining thermal stability of a storage carrier miniaturized by increasing capacity. Here, the nonvolatile memory element is usually electrically connected to a selection transistor, the nonvolatile memory element and the selection transistor constitute a memory cell, and a plurality of the memory cells constitutes a memory cell array. By the way, the larger a write current, the lower a data write failure ratio generated in the nonvolatile memory element. Therefore, the write current is preferably large. Therefore, it is preferable to increase a current that can flow through the selection transistor. However, a selection transistor that satisfies such a requirement has a problem that a channel forming region is large and it is difficult to reduce the memory cell. For example, Japanese Patent Application Laid-Open No. 2012-203964 discloses a technique in which a nonvolatile memory element and a selection transistor are alternately arranged in series to expand a