US-12628353-B2 - Package structure

US12628353B2US 12628353 B2US12628353 B2US 12628353B2US-12628353-B2

Abstract

A package structure is provided. The package structure includes a semiconductor substrate. The semiconductor substrate includes a lower portion and an upper portion. The upper portion of the semiconductor substrate defines a high speed signal transmission region. The high speed signal transmission region includes a first region configured to communicate with a first electronic component and a second region configured to communicate with an external device. The lower portion of the semiconductor substrate defines a power transmission region.

Inventors

Hai-Ming Chen
Hung-Yi Lin
Cheng-Yuan KUNG

Assignees

ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Dates

Publication Date: 20260512
Application Date: 20230308

Claims (16)

1 . A package structure, comprising: a semiconductor substrate comprising a lower portion and an upper portion; and wherein the upper portion of the semiconductor substrate defines a high speed signal transmission region, the high speed signal transmission region comprises a first region configured to communicate with a first electronic component and a second region configured to communicate with an external device, and wherein the lower portion of the semiconductor substrate defines a power transmission region, and wherein the semiconductor substrate comprises an application specific integrated circuit (ASIC), and the first electronic component comprises a memory die.
2 . The package structure of claim 1 , further comprising: a first conductive pillar electrically connected to a first conductive layer of the second region of the high speed signal transmission region, and the first conductive pillar extends along a lateral surface of the first electronic component.
3 . The package structure of claim 2 , wherein the external device is electrically connected to the first conductive pillar through a first redistribution structure disposed over the first conductive pillar.
4 . The package structure of claim 3 , further comprising: a second conductive pillar disposed under the semiconductor substrate and electrically connected to a second conductive layer of the power transmission region, wherein the second conductive pillar is configured to transmit a power to the first electronic component and the semiconductor substrate, and wherein the first conductive pillar has a first width, the second conductive pillar has a second width greater than the first width.
5 . The package structure of claim 2 , further comprising: a second conductive pillar disposed under the semiconductor substrate and electrically connected to a second conductive layer of the power transmission region, wherein the first conductive pillar is free from overlapping the second conductive pillar from a top view.
6 . The package structure of claim 2 , further comprising: a second conductive pillar disposed under the semiconductor substrate and electrically connected to a second conductive layer of the power transmission region; and a passive device disposed under the semiconductor substrate, wherein the second conductive pillar extends along a lateral surface of the passive device.
7 . The package structure of claim 6 , wherein the passive device comprises an inductor, and the package structure further comprises a third conductive pillar disposed between the second conductive pillar and the passive device, wherein the third conductive pillar is configured to function as a shield between the second conductive pillar and the passive device.
8 . The package structure of claim 1 , wherein the semiconductor substrate comprises a metal oxide semiconductor field effect transistor structure closer to the upper portion than to the lower portion.
9 . The package structure of claim 1 , wherein the first electronic component is connected to the semiconductor substrate through hybrid bonding.
10 . A package structure, comprising: a semiconductor substrate having a first surface and a second surface opposite to the first surface, wherein the semiconductor substrate comprises a high density conductive layer disposed adjacent to the first surface and a low density conductive layer disposed adjacent to the second surface, and wherein the high density conductive layer is configured to transmit a signal in communication with a first electronic component, and the low density conductive layer is configured to transmit a power to the semiconductor substrate.
11 . The package structure of claim 10 , further comprising: a plurality of first conductive pillars disposed over the first surface of the semiconductor substrate and electrically connected to the high density conductive layer; and a plurality of second conductive pillars disposed under the second surface of the semiconductor substrate and electrically connected to the low density conductive layer, wherein a first pitch of the plurality of first conductive pillars is less than a second pitch of the plurality of second conductive pillars.
12 . The package structure of claim 11 , wherein the first electronic component is disposed over the first surface and electrically connected to the high density conductive layer, and at least one of the plurality of first conductive pillars extends along a lateral surface of the first electronic component.
13 . The package structure of claim 11 , further comprising: an encapsulant encapsulating the semiconductor substrate, the plurality of first conductive pillars, and the plurality of second conductive pillars.
14 . The package structure of claim 13 , further comprising: a third conductive pillar encapsulated by the encapsulant, wherein the third conductive pillar is spaced apart from the plurality of first conductive pillars and the plurality of second conductive pillars.
15 . The package structure of claim 14 , wherein a width of the third conductive pillar is greater than a width of one of the plurality of first conductive pillars and a width of one of the plurality of second conductive pillars.
16 . A package structure, comprising: a semiconductor substrate having a first surface and a second surface opposite to the first surface, wherein the first surface of the semiconductor substrate defines a first signal transmission region configured to communicate with a first electronic component and a second signal transmission region configured to communicate with a second electronic component, and the second surface of the semiconductor substrate defines a power transmission region; and a first conductive pillar disposed over the first surface of the semiconductor substrate and located between the first electronic component and the second electronic component.

Description

BACKGROUND 1. Field of the Disclosure The present disclosure relates to a package structure, in particularly to a package structure including a semiconductor substrate which has I/O disposed at two opposite surfaces. 2. Description of the Related Art When different electronic components, such as a memory device (e.g., SRAM) and an application-specific integrated circuit (ASIC), are integrated, the distance therebetween may affect performance. To enhance the performance, face-to-face bonding of an ASIC with a memory device may be adopted to provide shorter transmission path. In such cases, a redistribution structure between the ASIC and the memory device may be needed due to the size difference between the bumps of the ASIC and the memory device, additional redistribution structures and conductive pillars may also needed to communicate the ASIC and the memory device to an external device or circuit. As a result, the manufacture cost and the thickness of the overall structure are increased. In order to provide the desired enhancement in performance, a new package structure is required. SUMMARY In some embodiments, a package structure includes a semiconductor substrate. The semiconductor substrate includes a lower portion and an upper portion. The upper portion of the semiconductor substrate defines a high speed signal transmission region. The high speed signal transmission region includes a first region configured to communicate with a first electronic component and a second region configured to communicate with an external device. The lower portion of the semiconductor substrate defines a power transmission region. In some embodiments, a package structure includes a semiconductor substrate. The semiconductor substrate has a first surface and a second surface opposite to the first surface. The semiconductor substrate includes a high density conductive layer disposed adjacent to the first surface and a low density conductive layer disposed adjacent to the second surface. In some embodiments, a package structure includes a semiconductor substrate having a first surface and a second surface opposite to the first surface. The first surface of the semiconductor substrate defines a first signal transmission region configured to communicate with a first electronic component and a second signal transmission region configured to communicate with a second electronic component. The second surface of the semiconductor substrate defines a power transmission region. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of some embodiments of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It is noted that various structures may not be drawn to scale, and dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a cross-sectional view of an example of a package structure according to some embodiments of the present disclosure. FIG. 2 illustrates a partial enlarged view of a substrate of a package structure according to some embodiments of the present disclosure. FIG. 3 illustrates a cross-sectional view of an example of a package structure according to some embodiments of the present disclosure. FIG. 4 illustrates a cross-sectional view of an example of a package structure according to some embodiments of the present disclosure. FIG. 5 illustrates a cross-sectional view of an example of a package structure according to some embodiments of the present disclosure. FIG. 6 illustrates a cross-sectional view of a package structure according to some embodiments of the present disclosure. FIG. 7 illustrates a cross-sectional view of a package structure according to some embodiments of the present disclosure. FIG. 8 illustrates a cross-sectional view of an example of a package structure according to some embodiments of the present disclosure. FIG. 9A illustrates a layout of conductive pillars of a package structure according to some embodiments of the present disclosure. FIG. 9B illustrates a layout of conductive pillars of a package structure according to some embodiments of the present disclosure. FIG. 9C illustrates a layout of conductive pillars of a package structure according to some embodiments of the present disclosure. FIG. 10A illustrates a layout of a conductive pillar(s) and an electronic component of a package structure according to some embodiments of the present disclosure. FIG. 10B illustrates a layout of a conductive pillar(s) and an electronic component of a package structure according to some embodiments of the present disclosure. FIG. 10C illustrates a layout of a conductive pillar(s) and an electronic component of a package structure according to some embodiments of the present disclosure. FIG. 11A illustrates one or more stages of an example of a method for manufacturing a package structure according to some embodiments of the present disclosure. FIG. 11B illustrates one or more s